Chein-Wei Jen

70 papers A 5C 11Misc 7Journal 23Unranked 24
YearRankTypeTitle / Venue / Authors
2007 C conf
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.
ISCAS
Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2006 — conf
A 52mW 1200MIPS compact DSP for multi-core media SoC.
ASP-DAC
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2006 A conf
PAC DSP Core and Application Processors.
ICME
David Chih-Wei Chang, I-Tao Liao, Jenq Kuen Lee, Wen-Feng Chen, Shau-Yin Tseng, Chein-Wei Jen
2006 C conf
Programmable FIR filter with adder-based computing engine.
ISCAS
Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
2005 J jnl
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform.
IEEE Trans. Circuits Syst. Video Technol.
Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
2005 J jnl
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Technol.
Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
2005 — conf
A unified processor architecture for RISC & VLIW DSP.
ACM Great Lakes Symposium on VLSI
Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
2005 J jnl
An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC.
IEEE Trans. Circuits Syst. Video Technol.
Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen
2005 A conf
Architecture for area-efficient 2-D transform in H.264/AVC.
ICME
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2005 — conf
Hierarchical instruction encoding for VLIW digital signal processors.
ISCAS (4)
Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
2005 — conf
Pipelining technique for energy-aware datapaths.
ISCAS (2)
Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
2005 J jnl
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning.
IEICE Trans. Electron.
Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen
2004 — conf
A bandwidth and memory efficient MPEG-4 shape encoder.
ASP-DAC
Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
2004 — conf
A compact DSP core with static floating-point unit & its microcode generation.
ACM Great Lakes Symposium on VLSI
Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2004 — conf
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization.
ISCAS (2)
Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen
2004 — conf
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding.
ISCAS (2)
Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
2004 J jnl
Optimal frame memory and data transfer scheme for MPEG-4 shape coding.
IEEE Trans. Consumer Electron.
Kun-Bin Lee, Hao-Yun Chin, Nelson Yen-Chung Chang, Hui-Cheng Hsu, Chein-Wei Jen
2004 — conf
QME: an efficient subsampling-based block matching algorithm for motion estimation.
ISCAS (2)
Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
2004 — conf
Static floating-point unit with implicit exponent tracking for embedded DSP.
ISCAS (2)
Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
2004 — conf
Trace-path analysis and performance estimation for multimedia application in embedded system.
ISCAS (2)
Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen
2003 — conf
A memory efficient realization of cyclic convolution and its application to discrete cosine transform.
ISCAS (4)
Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
2003 C conf
An Efficient VLIW DSP Architecture for Baseband Processing.
ICCD
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
2003 — conf
Area-effective FIR filter design for multiplier-less implementation.
ISCAS (5)
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
2003 A conf
Coefficient optimization for area-effective multiplier-less FIR filters.
ICME
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
2003 J jnl
Edge-preserving texture filtering for real-time rendering.
Vis. Comput.
Yuan-Chung Lee, Chein-Wei Jen
2003 J jnl
Generalized Earliest-First Fast Addition Algorithm.
IEEE Trans. Computers
Wen-Chang Yeh, Chein-Wei Jen
2003 J jnl
High-speed and low-power split-radix FFT.
IEEE Trans. Signal Process.
Wen-Chang Yeh, Chein-Wei Jen
2003 A conf
Performance evaluation of ring-structure register file in multimedia applications.
ICME
Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen
2002 — conf
A new group distributed arithmetic design for the one dimensional discrete Fourier transform.
ISCAS (1)
Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
2002 — conf
CASCADE - configurable and scalable DSP environment.
ISCAS (4)
Tay-Jyi Lin, Chein-Wei Jen
2002 — conf
High-speed memory-saving architecture for the embedded block coding in JPEG2000.
ISCAS (5)
Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen
2002 J jnl
Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system.
IEEE Trans. Multim.
Bor-Sung Liang, Yuan-Chung Lee, Wen-Chang Yeh, Chein-Wei Jen
2002 J jnl
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture.
IEEE Trans. Circuits Syst. Video Technol.
Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen
2001 — conf
An efficient 2-D DWT architecture via resource cycling.
ISCAS (4)
Tay-Jyi Lin, Chein-Wei Jen
2001 — conf
Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing.
ISCAS (2)
Yuan-Chung Lee, Chein-Wei Jen
2001 J jnl
Improved quadratic normal vector interpolation for realistic shading.
Vis. Comput.
Yuan-Chung Lee, Chein-Wei Jen
2001 — conf
Power modeling and low-power design of content addressable memories.
ISCAS (4)
Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen
2000 Misc conf
A high performance carry-save to signed-digit recoder for fused addition-multiplication.
ICASSP
Wen-Chang Yeh, Chein-Wei Jen
2000 C conf
A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers.
ISCAS
Ilion Yi-Liang Hsiao, Chein-Wei Jen
2000 J jnl
A simple processor core design for DCT/IDCT.
IEEE Trans. Circuits Syst. Video Technol.
Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen
2000 J jnl
Computation-effective 3-D graphics rendering architecture for embedded multimedia system.
IEEE Trans. Consumer Electron.
Bor-Sung Liang, Chein-Wei Jen
2000 C conf
Deferred lighting: a computation-efficient approach for real-time 3-D graphics.
ISCAS
Bor-Sung Liang, Wen-Chang Yeh, Yuan-Chung Lee, Chein-Wei Jen
2000 J jnl
High-Speed Booth Encoded Parallel Multiplier Design.
IEEE Trans. Computers
Wen-Chang Yeh, Chein-Wei Jen
2000 C conf
Motion estimation using on-line arithmetic.
ISCAS
Ching-Long Su, Chein-Wei Jen
2000 C conf
On-Line Polygon Refining Using a Low Computation Subdivision Algorithm.
GMP
Yuan-Chung Lee, Chein-Wei Jen
1999 — conf
Bus buffer modeling and optimization in video processing IP.
ICECS
Kun-Bin Lee, Chia-Hsing Lin, Chein-Wei Jen
1998 — conf
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement.
Great Lakes Symposium on VLSI
Jen-Chien Tuan, Chein-Wei Jen
1998 Misc conf
Low power FIR filter realization with differential coefficients and input.
ICASSP
Tian-Sheuan Chang, Chein-Wei Jen
1996 — conf
A programmable concurrent video signal processor.
ICIP (2)
Chih-Chin Chen, Chein-Wei Jen
1996 J jnl
VASS - A VLSI array system synthesizer.
J. VLSI Signal Process.
Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen
1995 J jnl
Scalable array architecture design for full search block matching.
IEEE Trans. Circuits Syst. Video Technol.
Shifan Chang, Juin-Haur Hwang, Chein-Wei Jen
1994 C conf
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform.
ISCAS
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1994 J jnl
A motion detection scheme for motion adaptive pro-scan conversion.
Signal Process. Image Commun.
Shifan Chang, Chein-Wei Jen, Charng Long Lee
1994 — conf
A novel VLSI array design for the discrete Hartley transform using cyclic convolution.
ICASSP (2)
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1993 C conf
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform.
ISCAS
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1993 C conf
A High Throughput Systolic Design for QR Algorithm.
ISCAS
Jiann-Jenn Wang, Chein-Wei Jen
1993 C conf
A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
ISCAS
Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
1993 J jnl
A New Array Architecture for Prime-Length Discrete Cosine Transform.
IEEE Trans. Signal Process.
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1993 J jnl
Binary partition algorithms and VLSI architectures for median and rank order filtering.
IEEE Trans. Signal Process.
Chamg Long Lee, Chein-Wei Jen
1992 Misc conf
A memory-based approach to design and implement systolic arrays for DFT and DCT.
ICASSP
Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
1992 J jnl
A parallel adaptive algorithm for moving target detection and its VLSI array realization.
IEEE Trans. Signal Process.
Chi-Min Liu, Chein-Wei Jen
1992 J jnl
Data Flow Representation of Iterative Algorithms for Systolic Arrays.
IEEE Trans. Computers
Chein-Wei Jen, Ding-Ming Kwai
1992 J jnl
Design of Two-Level Pipelined Systolic Array and its Application to Image.
J. Circuits Syst. Comput.
Chein-Wei Jen, Chi-Min Liu
1992 Misc conf
Efficient synthesis and high-speed implementation of look-ahead recursive filters.
ICASSP
Chien-Piao Lan, Shih-Chieh Wen, Chein-Wei Jen
1991 Misc conf
A high-level synthesizer for VLSI array architectures dedicated to digital signal processing.
ICASSP
Tung-Hao Huang, Chi-Min Liu, Chein-Wei Jen
1990 Misc conf
Parallel adaptive algorithm for moving target indicator and its VLSI array realization.
ICASSP
Chi-Min Liu, Bor-Shyong Yang, Chein-Wei Jen
1990 — conf
Recursive algorithms for AR spectral estimation and their array realizations.
ASAP
Chi-Min Liu, Chein-Wei Jen
1989 J jnl
Multi-dimensional parallel computing structures for regular iterative algorithms.
Integr.
Chein-Wei Jen, Ding-Ming Kwai
1989 Misc conf
Two-level pipeline design for image resampling.
ICASSP
Chein-Wei Jen, Chi-Min Liu
1986 A conf
Real-Time Configuration for Fault-Tolerant VLSI Array Processors.
RTSS
Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen