Chee-Kian Ong

12 papers A 3Misc 3Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2008 J jnl
A Clock-Less Jitter Spectral Analysis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
2006 J jnl
Bit-Error-Rate Estimation for High-Speed Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng
2004 Misc conf
A Scalable On-Chip Jitter Extraction Technique.
VTS
Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
2004 J jnl
A new sigma-delta modulator architecture for testing using digital stimulus.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chee-Kian Ong, Kwang-Ting Cheng, Li-C. Wang
2004 A conf
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics.
ITC
Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng
2004 — conf
Jitter spectral extraction for multi-gigahertz signal.
ASP-DAC
Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
2004 A conf
Random Jitter Extraction Technique in a Multi-Gigahertz Signal.
DATE
Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
2003 — conf
Delta-sigma modulator based mixed-signal BIST architecture for SoC.
ASP-DAC
Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang
2002 Misc conf
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus.
VTS
Chee-Kian Ong, Kwang-Ting (Tim) Cheng
2000 A conf
A BIST Scheme for On-Chip ADC and DAC Testing.
DATE
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
2000 — conf
An FPGA-based re-configurable functional tester for memory chips.
Asian Test Symposium
Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
2000 Misc conf
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.
VTS
Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng