Che-Fu Liang

16 papers Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Implementation of transformer-based LLMs with large-scale optoelectronic neurons on a CMOS image sensor platform.
CoRR
Neil Na, Chih-Hao Cheng, Shou-Chen Hsu, Che-Fu Liang, Chung-Chih Lin, Nathaniel Y. Na, Andrew I. Shieh, Erik Chen, Haisheng Rong, Richard A. Soref
2015 — conf
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter.
ISSCC
Che-Fu Liang, Ping-Ying Wang
2015 — conf
A 1V fractional-N PLL with nonlinearity-insensitive modulator.
A-SSCC
Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang
2014 — conf
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO.
ISSCC
Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang
2013 — conf
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation.
ISSCC
Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn
2011 — conf
An injection-locked ring PLL with self-aligned injection window.
ISSCC
Che-Fu Liang, Keng-Jan Hsiao
2009 J jnl
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu
2008 J jnl
10-Gb/s Inductorless CDRs With Digital Frequency Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Che-Fu Liang, Hong-Lin Chu, Shen-Iuan Liu
2008 — conf
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells.
ISSCC
Che-Fu Liang, Shen-Iuan Liu
2008 J jnl
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems.
IEEE J. Solid State Circuits
Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu
2008 J jnl
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.
IEEE J. Solid State Circuits
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2007 J jnl
A Multi-Band Burst-Mode Clock and Data Recovery Circuit.
IEICE Trans. Electron.
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2007 J jnl
Spur-Suppression Techniques for Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs
Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu
2006 — conf
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS.
CICC
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2006 — conf
A 14-band Frequency Synthesizer for MB-OFDM UWB Application.
ISSCC
Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma
2006 J jnl
A Calibrated Pulse Generator for Impulse-Radio UWB Applications.
IEEE J. Solid State Circuits
Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu