Chaudhry Indra Kumar

13 papers Misc 1Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2024 Misc conf
A High Performance and Low Power Subthreshold Voltage Level Shifter Design.
VLSID
Ananya Kapoor, Ayush Thapar, Chaitanya Shanker Jha, Chaudhry Indra Kumar
2024 — conf
A Radiation-Hardened Double Node Upset Latch Design for Nanoscale CMOS Technologies.
COMPENG
Promit Mandal, Prince Kumar, Saarthak Vijay Singh, Chaudhry Indra Kumar
2024 J jnl
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications.
Integr.
Chaudhry Indra Kumar, Abhishek Chaudhary, Shreyansh Upadhyaya
2022 J jnl
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN.
IEEE Trans. Circuits Syst. II Express Briefs
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022 J jnl
An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design.
J. Circuits Syst. Comput.
Chaudhry Indra Kumar
2022 J jnl
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications.
Integr.
Raghav Shekhar, Chaudhry Indra Kumar
2019 J jnl
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.
IEEE Trans. Very Large Scale Integr. Syst.
Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu
2019 J jnl
An energy-efficient variation aware self-correcting latch.
Microelectron. J.
Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu
2019 J jnl
High performance energy efficient radiation hardened latch for low voltage applications.
Integr.
Chaudhry Indra Kumar, Anand Bulusu
2018 — conf
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability.
PRIME
Chaudhry Indra Kumar, Anand Bulusu
2016 — conf
A novel energy-efficient self-correcting methodology employing INWE.
SMACD
Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
2011 — conf
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique.
ISED
Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor
2011 — conf
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance.
ISVLSI
Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik