Chauchin Su - RankMe

75 papers A 10B 1C 6Misc 3Journal 29Unranked 26

Year	Rank	Type	Title / Venue / Authors
2019	A	`conf`	Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. DATE Ting-You Lin, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang
2017	J	`jnl`	LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs. Sensors Ting-You Lin, Yingchieh Ho, Chauchin Su
2016	—	`conf`	A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system. ISOCC Yuhwai Tseng, Ting-You Lin, Songwen Yau, Yingchieh Ho, Chauchin Su
2014	J	`jnl`	A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. IEEE J. Solid State Circuits Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee
2014	—	`conf`	A low-power analog-to-digital converter with digitalized amplifier for PAM systems. MWSCAS Yingchieh Ho, Chou-Ming Kuo, Chauchin Su
2013	J	`jnl`	A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO. IEEE J. Solid State Circuits Yingchieh Ho, Yu-Sheng Yang, Chiachi Chang, Chauchin Su
2012	J	`jnl`	A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording. IEEE Trans. Biomed. Circuits Syst. Yuhwai Tseng, Yingchieh Ho, Shuoting Kao, Chauchin Su
2012	J	`jnl`	A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. IEEE J. Solid State Circuits Yingchieh Ho, Chauchin Su
2012	—	`conf`	A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee
2012	J	`jnl`	Cumulative Differential Nonlinearity Testing of ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hung-Kai Chen, Yingchieh Ho, Chauchin Su
2012	J	`jnl`	Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs Yingchieh Ho, Chiachi Chang, Chauchin Su
2012	J	`jnl`	Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers. IEEE J. Emerg. Sel. Topics Circuits Syst. Yingchieh Ho, Hung-Kai Chen, Chauchin Su
2011	—	`conf`	A 0.2-0.6 V ring oscillator design using bootstrap technique. A-SSCC Yingchieh Ho, Yu-Sheng Yang, Chauchin Su
2010	C	`conf`	A 5Gb/s pulse signaling interface for low power on-chip data communication. ISCAS Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su
2010	J	`jnl`	Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Trans. Inf. Syst. Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
2010	J	`jnl`	Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
2010	J	`jnl`	Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks. IEEE Trans. Instrum. Meas. Jen-Chien Hsu, Chauchin Su
2009	J	`jnl`	A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. Circuits Syst. I Regul. Pap. Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
2009	J	`jnl`	A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2009	J	`jnl`	Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Trans. Commun. Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
2009	J	`jnl`	Design of an All-Digital LVDS Driver. IEEE Trans. Circuits Syst. I Regul. Pap. Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu
2008	J	`jnl`	A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Briefs Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
2008	—	`conf`	A scalable digitalized buffer for gigabit I/O. CICC Hungwen Lu, Chauchin Su, Chien-Nan Liu
2008	J	`jnl`	BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops. IEEE Trans. Instrum. Meas. Jen-Chien Hsu, Chauchin Su
2008	J	`jnl`	Long-Range Prediction for Real-Time MPEG Video Traffic: An H IEEE Trans. Circuits Syst. Video Technol. Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su
2007	—	`conf`	A Test and Diagnosis Methodology for RF Transceivers. ATS Hung-Kai Chen, Chauchin Su
2007	J	`jnl`	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	J	`jnl`	Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2006	—	`conf`	A Digital BIST Methodology for Spread Spectrum Clock Generators. ATS Maohsuan Chou, Jen-Chien Hsu, Chauchin Su
2006	B	`conf`	Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. SMC Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu
2006	J	`jnl`	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
2006	—	`conf`	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2006	J	`jnl`	Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Trans. Electron. Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su
2005	—	`conf`	A spread spectrum clock generator for SATA-II. ISCAS (3) Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su
2005	—	`conf`	Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Multilevel full-chip routing with testability and yield enhancement. SLIP Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Oscillation ring based interconnect test scheme for SOC. ASP-DAC Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2004	—	`conf`	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2003	Misc	`conf`	1149.4 Based On-Line Quiescent State Monitoring Technique. VTS Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng
2003	—	`conf`	A novel LCD driver testing technique using logic test channels. ASP-DAC Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng
2002	J	`jnl`	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen
2001	—	`conf`	A computer aided engineering system for memory BIST. ASP-DAC Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee
2001	A	`conf`	Configuration free SoC interconnect BIST methodology. ITC Chauchin Su, Wenliang Tseng
2001	J	`jnl`	Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2001	J	`jnl`	Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
2001	Misc	`conf`	Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. VTS Yue-Tsang Chen, Chauchin Su
2000	J	`jnl`	A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
2000	—	`conf`	A methodology for fault model development for hierarchical linear systems. Asian Test Symposium Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
2000	A	`conf`	All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
2000	Misc	`conf`	Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. VTS Chauchin Su, Yue-Tsang Chen
2000	—	`conf`	Fault diagnosis for linear analog circuits. Asian Test Symposium Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2000	J	`jnl`	Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. J. Inf. Sci. Eng. Chauchin Su, Yue-Tsang Chen, Shenshung Chiang
2000	J	`jnl`	Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chauchin Su, Yue-Tsang Chen
2000	—	`conf`	Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
1999	—	`conf`	Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium Chauchin Su, Yue-Tsang Chen, Chung-Len Lee
1999	J	`jnl`	Decentralized BIST Methodology for System Level Interconnects. J. Electron. Test. Chauchin Su, Shyh-Jye Jou
1998	A	`conf`	A linear optimal test generation algorithm for interconnect testing. ICCAD Chauchin Su
1998	—	`conf`	Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. Asian Test Symposium Yue-Tsang Chen, Chauchin Su
1998	A	`conf`	Boundary scan BIST methodology for reconfigurable systems. ITC Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen
1998	—	`conf`	Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. Asian Test Symposium Chauchin Su, Yue-Tsung Chen
1997	—	`conf`	Analog signal metrology for mixed signal ICs. Asian Test Symposium Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen
1997	A	`conf`	Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
1997	—	`conf`	Structural approach for performance driven ECC circuit synthesis. ASP-DAC Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou
1996	—	`conf`	Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. ED&TC Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting
1996	A	`conf`	Metrology for analog module testing using analog testability bus. ICCAD Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
1996	—	`conf`	Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting
1995	C	`conf`	A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su
1995	C	`conf`	Circuits Design Optimization Using Symbolic Approach. ISCAS Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su
1995	A	`conf`	Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD Chauchin Su, Shenshung Chiang, Shyh-Jye Jou
1994	A	`conf`	An I ITC Chauchin Su, Kychin Hwang, Shyh-Jye Jou
1994	C	`conf`	Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang
1994	—	`conf`	Random Testing of Interconnects in A Boundary Scan Environment. EDAC-ETC-EUROASIC Chauchin Su
1993	A	`conf`	A Serial-Scan Test-Vector-Compression Methodology. ITC Chauchin Su, Kychin Hwang
1993	C	`conf`	A Universal BIST Methodology for Interconnects. ISCAS Chiyuan Chang, Chauchin Su
1993	C	`conf`	ECCSyn: a Synthesis Tool for ECC Circuits. ISCAS Chauchin Su, Jyrghong Wang