Chau-Chin Huang

12 papers A* 5A 2Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2020 J jnl
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo
2020 A* conf
Latch Clustering for Timing-Power Co-Optimization.
DAC
Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang
2018 — conf
End-to-End Industrial Study of Retiming.
ISVLSI
Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli
2018 J jnl
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany
2017 A conf
Clock-aware placement for large-scale heterogeneous FPGAs.
ICCAD
Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo
2017 A* conf
Graph-Based Logic Bit Slicing for Datapath-Aware Placement.
DAC
Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang
2016 A* conf
Timing-driven cell placement optimization for early slack histogram compression.
DAC
Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo
2015 A conf
Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.
ICCAD
Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
2015 — conf
Detailed-Routing-Driven analytical standard-cell placement.
ASP-DAC
Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang
2014 J jnl
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang
2014 A* conf
Routability-Driven Blockage-Aware Macro Placement.
DAC
Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang
2013 A* conf
Routability-driven placement for hierarchical mixed-size circuit designs.
DAC
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang