Charvaka Duvvury

16 papers C 1Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
Analysis of VF-TLP ESD Measurements Using Machine Learning.
ISQED
Seyed Hossein Hosseini, Mehrdad Nourani, Theo Smedes, Charvaka Duvvury
2015 J jnl
System efficient ESD design.
Microelectron. Reliab.
Harald Gossner, Charvaka Duvvury
2006 — conf
Circuit design issues in multi-gate FET CMOS technologies.
ISSCC
Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer
2006 J jnl
Gate oxide failures due to anomalous stress from HBM ESD testers.
Microelectron. Reliab.
Charvaka Duvvury, Robert Steinhoff, Gianluca Boselli, Vijay Reddy, Hans Kunz, Steve Marum, Roger Cline
2005 J jnl
Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies.
Microelectron. Reliab.
Gianluca Boselli, Charvaka Duvvury
2004 J jnl
Latchup in voltage tolerant circuits: a new phenomenon.
Microelectron. Reliab.
Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez
2002 J jnl
Development of substrate-pumped nMOS protection for a 0.13 mum technology.
Microelectron. Reliab.
Craig Salling, Jerry Hu, Jeff Wu, Charvaka Duvvury, Roger Cline, Rith Pok
2002 — conf
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract).
ISQED
Charvaka Duvvury
2001 J jnl
A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies.
Microelectron. Reliab.
Steven H. Voldman, W. Anderson, R. Ashton, M. Chaine, Charvaka Duvvury, T. Maloney, E. Worley
2001 — conf
ESD protection device issues for IC designs.
CICC
Charvaka Duvvury
2001 — conf
Issues in Deep Submicron State-of-the-Art ESD Design.
ISQED
Charvaka Duvvury
2000 — conf
ESD: Design For IC Chip Quality and Reliability.
ISQED
Charvaka Duvvury
1994 J jnl
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
1993 J jnl
ESD: a pervasive reliability concern for IC technologies.
Proc. IEEE
Charvaka Duvvury, Ajith Amerasekera
1993 C conf
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.
ISCAS
Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang
1992 J jnl
Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation.
IEEE J. Solid State Circuits
S. Aur, Charvaka Duvvury, Hugh McAdams, C. Perrin