Charlie Chung-Ping Chen

91 papers A* 6A 15C 13Misc 1Journal 20Unranked 35

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Intelligent Design Automation for Heterogeneous Integration. ISPD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
2021	A	`conf`	Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen
2020	J	`jnl`	A Quasi-V IEEE Trans. Circuits Syst. II Express Briefs Chung-Yi Ting, Jing-Yuan Lin, Charlie Chung-Ping Chen
2019	J	`jnl`	A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique. IEEE Trans. Circuits Syst. II Express Briefs Yi-Chieh Hsu, Chung-Yi Ting, Li-Sheng Hsu, Jing-Yuan Lin, Charlie Chung-Ping Chen
2018	—	`conf`	A Real Time EEG Analysis System for the Prediction of Clinical Antidepressant Responses. DSP Shuo-Hong Hung, Ina Wu, Yi-Chen Li, Cheng-Ta Li, Charlie Chung-Ping Chen
2016	J	`jnl`	A 6.7 MHz to 1.24 GHz 0.0318 mm IEEE J. Solid State Circuits Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2016	A	`conf`	Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. DATE Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen
2015	—	`conf`	A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique. VLSIC Kuan-I Wu, I-Shing Shen, Christina F. Jou, Charlie Chung-Ping Chen
2015	C	`conf`	A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. ISCAS Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen
2015	C	`conf`	A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. ISCAS Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
2015	C	`conf`	A fast-settling high linearity auto gain control for broadband OFDM-based PLC system. ISCAS Kuan-I Wu, Szu-Yao Hung, Shuo-Hong Hung, Charlie Chung-Ping Chen
2014	—	`conf`	An efficient multi-touch tracking algorithm with a large number of points. ICCE-Berlin Shih-Lun Huang, Sheng-Yi Hung, Charlie Chung-Ping Chen, Cheng-Han Tsao, Nai-Wen Chang
2014	—	`conf`	Cost-efficient hardware implementation of stereo image depth optimization system. IC3D Chun-Chang Yu, Chia-Hao Cheng, Pei-Chun Lin, Charlie Chung-Ping Chen
2014	C	`conf`	Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation. ISCAS Kuan-I Wu, Shuo-Hong Hung, Shang-Yu Shieh, Bor-Tsang Hwang, Szu-Yao Hung, Charlie Chung-Ping Chen
2013	C	`conf`	A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. ISCAS Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen
2013	C	`conf`	A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. ISCAS Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
2013	C	`conf`	A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system. ISCAS Szu-Yao Hung, Kai-Hsiang Chan, Charlie Chung-Ping Chen
2012	C	`conf`	A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. ISCAS Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen
2012	—	`conf`	A 6.7MHz-to-1.24GHz 0.0318mm ISSCC Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2012	J	`jnl`	An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
2012	J	`jnl`	Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
2011	C	`conf`	A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. ISCAS Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen
2011	C	`conf`	A 12 Gb/s chip-to-chip AC coupled transceiver. ISCAS Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen
2011	—	`conf`	An at-speed self-testable technique for the high speed domino adder. CICC Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen
2010	J	`jnl`	Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen
2010	—	`conf`	Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu
2010	—	`conf`	The compatibility analysis of thread migration and DVFS in multi-core processor. ISQED Dongkeun Oh, Charlie Chung-Ping Chen, Nam Sung Kim, Yu Hen Hu
2008	A*	`conf`	Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. DAC Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen
2008	—	`conf`	An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng
2008	—	`conf`	LTCC spiral inductor modeling, synthesis, and optimization. ASP-DAC Tuck Boon Chan, Hsinchia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen
2008	—	`conf`	Process-Variation Statistical Modeling for VLSI Timing Analysis. ISQED Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen
2008	—	`ch.`	Wire Sizing. Handbook of Algorithms for Physical Design Automation Sanghamitra Roy, Charlie Chung-Ping Chen
2007	—	`conf`	3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. ISQED Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
2007	J	`jnl`	Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu
2007	—	`conf`	SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC Sanghamitra Roy, Charlie Chung-Ping Chen
2006	—	`conf`	Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
2006	—	`conf`	ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED Sanghamitra Roy, Charlie Chung-Ping Chen
2006	J	`jnl`	Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
2006	—	`conf`	Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. ISPD Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen
2006	C	`conf`	Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2006	J	`jnl`	Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
2006	A	`conf`	Statistical timing analysis with path reconvergence and spatial correlations. DATE Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
2006	J	`jnl`	Temperature-Aware Placement for SOCs. Proc. IEEE Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
2005	—	`conf`	Block based statistical timing analysis with extended canonical timing model. ASP-DAC Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
2005	—	`conf`	Comprehensive frequency dependent interconnect extraction and evaluation methodology. ASP-DAC Rong Jiang, Charlie Chung-Ping Chen
2005	A*	`conf`	Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. DAC Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
2005	J	`jnl`	EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen
2005	A	`conf`	Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen
2005	Misc	`conf`	False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2005	—	`conf`	Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. ASP-DAC Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen
2005	J	`jnl`	HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen
2005	A*	`conf`	ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. DAC Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen
2005	—	`conf`	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC Jeng-Liang Tsai, Charlie Chung-Ping Chen
2005	A	`conf`	Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. DATE Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
2005	A	`conf`	System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). ICCAD Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li
2005	—	`conf`	Wave-pipelined on-chip global interconnect. ASP-DAC Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
2005	J	`jnl`	Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004	A	`conf`	A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004	—	`conf`	EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. CICC Rong Jiang, Charlie Chung-Ping Chen
2004	—	`conf`	Frequency-dependent reluctance extraction. ASP-DAC Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen
2004	A	`conf`	Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. DATE Rong Jiang, Charlie Chung-Ping Chen
2004	A	`conf`	SCORE: SPICE COmpatible Reluctance Extraction. DATE Rong Jiang, Charlie Chung-Ping Chen
2004	—	`conf`	SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. ISQED Ting-Yuan Wang, Charlie Chung-Ping Chen
2004	—	`conf`	Sensitivity guided net weighting for placement driven synthesis. ISPD Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2004	A*	`conf`	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. DAC Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
2004	A	`conf`	Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2004	J	`jnl`	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
2003	—	`conf`	3D thermal-ADI: an efficient chip-level transient thermal simulator. ISPD Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen
2003	—	`conf`	A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. ASP-DAC Yu-Min Lee, Charlie Chung-Ping Chen
2003	J	`jnl`	INDUCTWISE: inductance-wise interconnect simulator and extractor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
2003	—	`conf`	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
2003	—	`conf`	PODEA: Power delivery efficient analysis with realizable model reduction. ISCAS (4) Rong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen
2003	A	`conf`	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. ICCAD Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
2003	A	`conf`	The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . DATE Yu-Min Lee, Charlie Chung-Ping Chen
2003	J	`jnl`	The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Lee, Charlie Chung-Ping Chen
2003	J	`jnl`	Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. IEEE Trans. Very Large Scale Integr. Syst. Ting-Yuan Wang, Charlie Chung-Ping Chen
2002	J	`jnl`	3-D Thermal-ADI: a linear-time chip level transient thermal simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ting-Yuan Wang, Charlie Chung-Ping Chen
2002	—	`conf`	Future SoC Design Challenges and Solutions (invited). ISQED Charlie Chung-Ping Chen, Ed Cheng
2002	A*	`conf`	HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. DAC Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen
2002	A	`conf`	INDUCTWISE: inductance-wise interconnect simulator and extractor. ICCAD Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen
2002	—	`conf`	Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. ISQED Ting-Yuan Wang, Charlie Chung-Ping Chen
2002	J	`jnl`	Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Lee, Charlie Chung-Ping Chen
2002	J	`jnl`	Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong
2001	A*	`conf`	Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. DAC Tsung-Hao Chen, Charlie Chung-Ping Chen
2001	—	`conf`	Hierarchical model order reduction for signal-integrity interconnect synthesis. ACM Great Lakes Symposium on VLSI Yu-Min Lee, Charlie Chung-Ping Chen
2001	C	`conf`	Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. ICCD Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen
2001	—	`conf`	Optimal spacing and capacitance padding for general clock structures. ASP-DAC Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
2001	A	`conf`	Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. ICCAD Yu-Min Lee, Charlie Chung-Ping Chen
2001	C	`conf`	RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. ICCD Pradeepsunder Ganesh, Charlie Chung-Ping Chen
2001	—	`conf`	Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. ISPD Ting-Yuan Wang, Charlie Chung-Ping Chen
2000	A	`conf`	Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. ICCAD Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness