Charles Njinda

13 papers A* 3A 6Misc 1Journal 2Unranked 1

Year	Rank	Type	Title / Venue / Authors
2004	A	`conf`	A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. ITC Charles Njinda
1997	A*	`conf`	Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
1997	A	`conf`	How Seriously Do You Take Your Possible-Detect Faults? ITC Rajesh Raina, Charles Njinda, Robert F. Molyneaux
1995	A	`conf`	Performance Driven BIST Technique for Random Logic. ITC Charles Njinda, Neeraj Kaul
1994	A*	`conf`	Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
1994	J	`jnl`	SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1993	J	`jnl`	Generating a family of testable designs using the BILBO methodology. J. Electron. Test. Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
1992	A	`conf`	Optimal Sequencing of Scan Registers. ITC Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
1992	—	`conf`	SIESTA: a multi-facet scan design system. EURO-DAC Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer
1992	A*	`conf`	SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1991	A	`conf`	A Systematic Approach for Designing Testable VLSI Circuits. ICCAD Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
1991	Misc	`conf`	A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. VTS Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer
1991	A	`conf`	Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer