Charles J. Alpert

141 papers A* 23A 22C 2Journal 46Unranked 41

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2018	—	`conf`	Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
2017	—	`conf`	Modern Challenges in Constructing Clocks. ISPD Charles J. Alpert
2017	J	`jnl`	Stitch aware detailed placement for multiple E-beam lithography. Integr. Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey
2016	A	`conf`	MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	—	`conf`	Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2015	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey
2015	J	`jnl`	Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
2014	—	`conf`	Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
2014	J	`jnl`	Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2013	A	`conf`	CATALYST: planning layer directives for effective design closure. DATE Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
2013	A	`conf`	Clock power minimization using structured latch templates and decision tree induction. ICCAD Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
2013	A	`conf`	ICCAD-2013 CAD contest in placement finishing and benchmark suite. ICCAD Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert
2013	—	`conf`	Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2013	A*	`conf`	Routing congestion estimation with real design constraints. DAC Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
2013	J	`jnl`	Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2012	A*	`conf`	GLARE: global and local wiring aware routability evaluation. DAC Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2012	A*	`conf`	Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou
2012	A	`conf`	ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	—	`conf`	Keep it straight: teaching placement how to better handle designs with datapaths. ISPD Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2012	—	`conf`	MAPLE: multilevel adaptive placement for mixed-size designs. ISPD Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji
2012	A	`conf`	Placement: Hot or Not? ICCAD Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward
2012	A*	`conf`	The DAC 2012 routability-driven placement contest and benchmark suite. DAC Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
2012	—	`conf`	WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2011	J	`jnl`	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov
2011	—	`conf`	Quantifying academic placer performance on custom designs. ISPD Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.
2011	J	`jnl`	Shedding Physical Synthesis Area Bloat. VLSI Design Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan
2011	—	`conf`	The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy
2010	A	`conf`	Design-hierarchy aware mixed-size placement for routability optimization. ICCAD Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
2010	A*	`conf`	Detecting tangled logic structures in VLSI netlists. DAC Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn
2010	—	`conf`	ITOP: integrating timing optimization within placement. ISPD Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu
2010	A	`conf`	New placement prediction and mitigation techniques for local routing congestion. ICCAD Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji
2010	J	`jnl`	Speeding Up Physical Synthesis with Transactional Timing Analysis. IEEE Des. Test Comput. David A. Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov
2010	—	`conf`	Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou
2010	—	`conf`	What makes a design difficult to route. ISPD Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez
2009	J	`jnl`	A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. IEEE Trans. Circuits Syst. II Express Briefs Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	—	`conf`	A faster approximation scheme for timing driven minimum cost layer assignment. ISPD Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	A*	`conf`	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC Shiyan Hu, Zhuo Li, Charles J. Alpert
2009	A	`conf`	CRISP: Congestion reduction by iterated spreading during placement. ICCAD Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2009	—	`conf`	Ispd2009 clock network synthesis contest. ISPD Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert
2008	A	`conf`	A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD Shiyan Hu, Zhuo Li, Charles J. Alpert
2008	—	`conf`	Fast interconnect synthesis with layer assignment. ISPD Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia
2008	—	`book`	Handbook of Algorithms for Physical Design Automation. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
2008	—	`ch.`	Introduction to Physical Design. Handbook of Algorithms for Physical Design Automation Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
2008	A*	`conf`	Path smoothing via discrete optimization. DAC Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert
2008	—	`ch.`	Placement-Driven Synthesis Design Closure Tool. Handbook of Algorithms for Physical Design Automation Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi N. Reddy, Haoxing Ren, Louise Trevillyan
2008	A	`conf`	Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
2008	J	`jnl`	RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2008	—	`conf`	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2007	J	`jnl`	Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam
2007	J	`jnl`	Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
2007	—	`conf`	Fast Electrical Correction Using Resizing and Buffering. ASP-DAC Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
2007	—	`conf`	Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
2007	—	`ch.`	ISPD 2005/2006 Placement Benchmarks. Modern Circuit Placement Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia
2007	J	`jnl`	Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2007	—	`conf`	Probabilistic Congestion Prediction with Partial Blockages. ISQED Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
2007	A*	`conf`	RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
2007	J	`jnl`	Techniques for Fast Physical Synthesis. Proc. IEEE Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2007	A	`conf`	The coming of age of physical synthesis. ICCAD Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia
2007	—	`conf`	The nuts and bolts of physical synthesis. SLIP Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2006	J	`jnl`	A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
2006	J	`jnl`	Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2006	A*	`conf`	Fast algorithms for slew constrained minimum cost buffering. DAC Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2006	A*	`conf`	Timing-driven Steiner trees are (practically) free. DAC Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
2005	—	`conf`	A semi-persistent clustering technique for VLSI circuit placement. ISPD Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
2005	—	`conf`	An efficient surface-based low-power buffer insertion algorithm. ISPD Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
2005	A	`conf`	Computational geometry based placement migration. ICCAD Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan
2005	A*	`conf`	Diffusion-based placement migration. DAC Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
2005	—	`conf`	Making fast buffer insertion even faster via approximation techniques. ASP-DAC Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	A*	`conf`	Path based buffer insertion. DAC Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	—	`conf`	Placement stability metrics. ASP-DAC Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz
2005	A	`conf`	Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
2005	—	`conf`	The ISPD2005 placement contest and benchmark suite. ISPD Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
2004	J	`jnl`	A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
2004	—	`conf`	A fast algorithm for identifying good buffer insertion candidate locations. ISPD Charles J. Alpert, Milos Hrkic, Stephen T. Quay
2004	—	`conf`	A place and route aware buffered Steiner tree construction. ASP-DAC Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
2004	A	`conf`	Accurate estimation of global buffer delay within a floorplan. ICCAD Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2004	J	`jnl`	Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2004	J	`jnl`	Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2004	—	`conf`	Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC Weiping Shi, Zhuo Li, Charles J. Alpert
2004	A*	`conf`	Fast and flexible buffer trees that navigate the physical layout environment. DAC Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
2004	J	`jnl`	Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
2004	—	`ed.`	Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004 ISPD Charles J. Alpert, Patrick Groeneveld
2004	J	`jnl`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2003	J	`jnl`	A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2003	J	`jnl`	Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
2003	—	`conf`	Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2003	A*	`conf`	Delay and slew metrics using the lognormal distribution. DAC Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2003	J	`jnl`	Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
2003	J	`jnl`	Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Sachin S. Sapatnekar
2003	J	`jnl`	Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
2003	J	`jnl`	Optimal path routing in single- and multiple-clock domain systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Soha Hassoun, Charles J. Alpert
2003	—	`conf`	Porosity aware buffered steiner tree construction. ISPD Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
2003	—	`ed.`	Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003 ISPD Massoud Pedram, Charles J. Alpert
2002	A	`conf`	A delay metric for RC circuits based on the Weibull distribution. ICCAD Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
2002	—	`conf`	Buffer insertion with adaptive blockage avoidance. ISPD Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
2002	J	`jnl`	Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
2002	A	`conf`	Free space management for cut-based placement. ICCAD Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
2002	A	`conf`	Optimal buffered routing path constructions for single and multiple clock domain systems. ICCAD Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
2002	—	`conf`	PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2002	J	`jnl`	Probability-driven routing in a datapath environment. Integr. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
2002	—	`ed.`	Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 Timing Issues in the Specification and Synthesis of Digital Systems David P. LaPotin, Charles J. Alpert, John Lillis
2002	—	`conf`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2001	A*	`conf`	A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2001	J	`jnl`	A clock distribution network for microprocessors. IEEE J. Solid State Circuits Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie
2001	—	`conf`	Buffered Steiner trees for difficult instances. ISPD Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2001	J	`jnl`	Interconnect synthesis without wire tapering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
2001	A	`conf`	Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
2001	J	`jnl`	RC delay metrics for performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2001	J	`jnl`	Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2001	—	`conf`	Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2000	—	`conf`	A two moment RC delay metric for performance optimization. ISPD Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2000	A	`conf`	An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan
2000	—	`conf`	Datapath routing based on a decongestion metric. ISPD Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
2000	J	`jnl`	Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	J	`jnl`	Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. VLSI Design Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz
1999	A*	`conf`	Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	J	`jnl`	Buffer insertion for noise and delay optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	A	`conf`	Is wire tapering worthwhile? ICCAD Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	—	`conf`	Partitioning with terminals: a "new" problem and new benchmarks. ISPD Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
1999	J	`jnl`	Spectral Partitioning with Multiple Eigenvectors. Discret. Appl. Math. Charles J. Alpert, Andrew B. Kahng, So-Zen Yao
1998	A*	`conf`	Buffer Insertion for Noise and Delay Optimization. DAC Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1998	J	`jnl`	Faster minimization of linear wirelength for global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
1998	J	`jnl`	Multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
1998	—	`conf`	The ISPD98 circuit benchmark suite. ISPD Charles J. Alpert
1997	—	`conf`	Faster minimization of linear wirelength for global placement. ISPD Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan
1997	A*	`conf`	Multilevel Circuit Partitioning. DAC Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
1997	A*	`conf`	Quadratic Placement Revisited. DAC Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan
1997	A*	`conf`	Wire Segmenting for Improved Buffer Insertion. DAC Charles J. Alpert, Anirudh Devgan
1996	J	`jnl`	A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. Very Large Scale Integr. Syst. Charles J. Alpert, Andrew B. Kahng
1995	J	`jnl`	Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Andrew B. Kahng
1995	J	`jnl`	Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger
1995	J	`jnl`	Recent directions in netlist partitioning: a survey. Integr. Charles J. Alpert, Andrew B. Kahng
1995	A*	`conf`	Spectral Partitioning: The More Eigenvectors, The Better. DAC Charles J. Alpert, So-Zen Yao
1994	A	`conf`	A general framework for vertex orderings, with applications to netlist clustering. ICCAD Charles J. Alpert, Andrew B. Kahng
1994	A*	`conf`	Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC Charles J. Alpert, Andrew B. Kahng
1994	J	`jnl`	On the Minimum Density Interconnection Tree Problem. VLSI Design Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1993	C	`conf`	A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
1993	A*	`conf`	Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC Charles J. Alpert, Andrew B. Kahng
1993	C	`conf`	Minimum Density Interconneciton Trees. ISCAS Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh