Charles H. Stapper

20 papers A* 1Journal 16Unranked 3
YearRankTypeTitle / Venue / Authors
2000 J jnl
LSI yield modeling and process monitoring.
IBM J. Res. Dev.
Charles H. Stapper
1995 J jnl
Multipurpose DRAM architecture for optimal power, performance, and product flexibility.
IBM J. Res. Dev.
Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter
1994 J jnl
A statistical study of defect maps of large area VLSI IC's.
IEEE Trans. Very Large Scale Integr. Syst.
Israel Koren, Zahava Koren, Charles H. Stapper
1994 — conf
On Fractal Yield Models: A Statistical Paradox.
DFT
Charles H. Stapper, A. J. Rideout
1993 J jnl
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
IEEE Trans. Computers
Israel Koren, Zahava Koren, Charles H. Stapper
1993 J jnl
Improved Yield Models for Fault-Tolerant Memory Chips.
IEEE Trans. Computers
Charles H. Stapper
1993 — conf
Yield Model for ASIC and Processor Chips.
DFT
Charles H. Stapper, J. A. Patrick, R. J. Rosner
1992 — conf
A New Statistical Approach for Fault-Tolerant VLSI Systems.
FTCS
Charles H. Stapper
1992 J jnl
Synergistic Fault-Tolerance for Memory Chips.
IEEE Trans. Computers
Charles H. Stapper, Hsing-San Lee
1991 J jnl
High-speed on-chip ECC for synergistic fault-tolerance memory chips.
IEEE J. Solid State Circuits
John A. Fifield, Charles H. Stapper
1991 J jnl
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles H. Stapper
1990 J jnl
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC.
IEEE J. Solid State Circuits
Howard L. Kalter, Charles H. Stapper, John E. Barth Jr., John DiLorenzo, Charles E. Drake, John A. Fifield, Gordon A. Kelley, Scott C. Lewis, Willem B. van der Hoeven, James A. Yankosky
1989 J jnl
Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review.
IBM J. Res. Dev.
Charles H. Stapper
1989 J jnl
Simulation of spatial fault distributions for integrated circuit yield estimations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles H. Stapper
1986 A* conf
Yield of VLSI circuits: myths vs. reality (panel).
DAC
Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper
1984 J jnl
Modeling of Defects in Integrated Circuit Photolithographic Patterns.
IBM J. Res. Dev.
Charles H. Stapper
1984 J jnl
Yield Model for Fault Clusters Within Integrated Circuits.
IBM J. Res. Dev.
Charles H. Stapper
1983 J jnl
Modeling of Integrated Circuit Defect Sensitivities.
IBM J. Res. Dev.
Charles H. Stapper
1980 J jnl
Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product.
IBM J. Res. Dev.
Charles H. Stapper, A. N. McLaren, M. Dreckmann
1976 J jnl
LSI Yield Modeling and Process Monitoring.
IBM J. Res. Dev.
Charles H. Stapper