Charles Augustine

52 papers A* 3A 4B 1C 3Misc 2Journal 15Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	8.8 Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors. ISSCC Zakir K. Ahmed, Suhwan Kim, Charles Augustine, Harish K. Krishnamurthy, Krishnan Ravichandran, James W. Tschanz, Vivek De
2025	J	`jnl`	NEXUS: A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network With a Diamond Topology for Real-Time Data Processing. IEEE Trans. Biomed. Circuits Syst. Maryam Sadeghi, Yasser Rezaeiyan, Darío Fernández Khatiboun, Sherif Eissa, Federico Corradi, Charles Augustine, Farshad Moradi
2023	—	`conf`	A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
2023	J	`jnl`	Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das
2023	J	`jnl`	ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19. IEEE Des. Test Charles Augustine, Hai Helen Li
2022	A	`ed.`	ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022 ISLPED Hai Helen Li, Charles Augustine, Ayse Kivilcim Coskun, Swaroop Ghosh
2021	—	`conf`	All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid, A. Raman, K. Subramanian, Feroze Merchant, James W. Tschanz, Muhammad M. Khellah
2021	—	`conf`	Cache Compression with Efficient in-SRAM Data Comparison. NAS Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das
2021	Misc	`conf`	Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2020	—	`conf`	25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
2020	—	`conf`	2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2020	—	`conf`	A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
2020	J	`jnl`	A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. IEEE J. Solid State Circuits Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De
2020	—	`conf`	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
2019	—	`conf`	A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. VLSI Circuits Zakir K. Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De
2019	J	`jnl`	An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2019	A*	`conf`	Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2018	—	`conf`	An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	—	`conf`	Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. BioCAS Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2017	C	`conf`	Event-driven random backpropagation: Enabling neuromorphic deep learning machines. ISCAS Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
2017	J	`jnl`	Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection. CoRR Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2017	J	`jnl`	Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. CoRR Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci
2017	J	`jnl`	Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	—	`conf`	8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2016	J	`jnl`	Cache Design with Domain Wall Memory. IEEE Trans. Computers Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. CoRR Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
2016	J	`jnl`	Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016	—	`conf`	Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016	—	`conf`	Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. BioCAS Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2016	C	`conf`	Synaptic sampling in hardware spiking neural networks. ISCAS Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci
2015	—	`conf`	4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2015	—	`conf`	8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2014	—	`conf`	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2013	J	`jnl`	Dual pillar spin-transfer torque MRAMs for low power applications. ACM J. Emerg. Technol. Comput. Syst. Niladri Narayan Mojumder, Xuanyao Fong, Charles Augustine, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
2013	A	`conf`	Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
2012	A	`conf`	A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE Georgios Panagopoulos, Charles Augustine, Kaushik Roy
2012	A*	`conf`	Cognitive computing with spin-based neural networks. DAC Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	J	`jnl`	Proposal For Neuromorphic Hardware Using Spin Devices CoRR Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	B	`conf`	Spin based neuron-synapse module for ultra low power programmable computational networks. IJCNN Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	A	`conf`	TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2012	—	`conf`	Ultra low energy analog image processing using spin based neurons. NANOARCH Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2011	—	`conf`	Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
2011	—	`conf`	Low-power functionality enhanced computation architecture using spin-based devices. NANOARCH Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Kaushik Roy
2010	C	`conf`	A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS Georgios Karakonstantis, Charles Augustine, Kaushik Roy
2010	—	`conf`	Data-dependant sense-amplifier flip-flop for low power applications. CICC Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy
2009	—	`conf`	A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy
2009	—	`conf`	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy
2008	—	`conf`	Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT Nilanjan Banerjee, Charles Augustine, Kaushik Roy
2008	A*	`conf`	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
1992	Misc	`conf`	Testing generality in JANUS: a multi-lingual speech translation system. ICASSP Louise Osterholtz, Charles Augustine, Arthur E. McNair, Ivica Rogina, Hiroaki Saito, Tilo Sloboda, Joe Tebelskis, Alex Waibel