Chaolong Xu - RankMe

14 papers Journal 10Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A high speed and reflection cancel adaptive equalization using 4-tap floating FFE and 2-tap speculative pre-decision and loop-refactored DFE for wireline receiver. Microelectron. J. Xiaoyue Hu, Fangxu Lv, Jin Zhang, Jiaqing Xu, Qiang Wang, Cewen Liu, Chaolong Xu, Zhouhao Yang, Jinwen Li
2026	J	`jnl`	Degradation-aware deep unfolding network with multi-loss optimization for underwater image enhancement. Appl. Soft Comput. Chaolong Xu, Zhibin Xie, Peiyu Yan, Xin Shu, Changbin Shao
2025	J	`jnl`	A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. IEEE Trans. Very Large Scale Integr. Syst. Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang
2025	J	`jnl`	A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver. Microelectron. J. Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai
2025	J	`jnl`	A lightweight underwater object detection with enhanced detail and edge-aware feature fusion. Digit. Signal Process. Chaolong Xu, Zhibin Xie
2025	J	`jnl`	An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang
2025	—	`conf`	Real-Time Demonstration of FPGA-Based Advanced Equalizer with ZF-NL-RSSE for Data Center Interconnects. ECOC Zhouhao Yang, Fangxu Lv, Mingche Lai, Zhang Luo, Weixia Xu, Chaolong Xu, Kefan Ma, Xiaoyue Hu, Cewen Liu, Zheng Peng, Xianchao Zeng
2024	J	`jnl`	A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE. IEICE Electron. Express Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu
2024	—	`conf`	A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver. A-SSCC Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu
2024	—	`conf`	FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang
2024	J	`jnl`	Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
2023	—	`conf`	A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu
2022	J	`jnl`	A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2022	J	`jnl`	A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu