Chao-Yang Yeh

11 papers A* 1A 4Journal 2Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	10.2 A Dynamic Performance Augmentation in a 3nm-Plus Mobile CPU. ISSCC Chien-Yu Lu, Bo-Jr Huang, Sung S.-Y. Hsueh, Trong-Hieu Tran, Eric Jia-Wei Fang, Chao-Yang Yeh, Quan Sun, Tao Chen, HsinChen Chen, Huaichung Chang, C.-J. Tsai, Yi-Chang Zhuang, Barry Chen, Ericbill Wang, Hugh Mair, Shih-Arn Hwang
2022	—	`conf`	A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. ISSCC Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang
2007	J	`jnl`	Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao-Yang Yeh, Malgorzata Marek-Sadowska
2006	—	`conf`	Clock Distribution Architectures: A Comparative Study. ISQED Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
2005	A	`conf`	A sliding window scheme for accurate clock mesh analysis. ICCAD Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
2005	A	`conf`	Skew-programmable clock design for FPGA and skew-aware placement. FPGA Chao-Yang Yeh, Malgorzata Marek-Sadowska
2005	A	`conf`	Timing-aware power noise reduction in layout. ICCAD Chao-Yang Yeh, Malgorzata Marek-Sadowska
2004	J	`jnl`	Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	A*	`conf`	Delay budgeting in sequential circuit with application on FPGA placement. DAC Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	A	`conf`	Minimum-Area Sequential Budgeting for FPGA. ICCAD Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	—	`conf`	Sequential delay budgeting with interconnect prediction. SLIP Chao-Yang Yeh, Malgorzata Marek-Sadowska