Chao-Wen Tzeng

19 papers A 2Journal 12Unranked 5
YearRankTypeTitle / Venue / Authors
2015 — conf
Case study of process and design performance debugging with Digital Speed Sensor.
VLSI-DAT
Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
2014 J jnl
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao
2013 J jnl
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst.
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013 — conf
Case study of yield learning through in-house flow of volume diagnosis.
VLSI-DAT
Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
2013 J jnl
Cell-Based Process Resilient Multiphase Clock Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng
2013 J jnl
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou
2013 J jnl
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.
IEEE Trans. Very Large Scale Integr. Syst.
Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang
2012 — conf
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.
VLSI-DAT
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng
2011 A conf
A fully cell-based design for timing measurement of memory.
ITC
Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao
2010 — conf
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
DFT
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010 J jnl
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Shi-Yu Huang
2009 J jnl
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang
2009 A conf
QC-Fill: An X-Fill method for quick-and-cool scan test.
DATE
Chao-Wen Tzeng, Shi-Yu Huang
2009 J jnl
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Shi-Yu Huang
2008 J jnl
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.
ACM Trans. Design Autom. Electr. Syst.
Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang
2008 — conf
Two-Gear Low-Power Scan Test.
ATS
Chao-Wen Tzeng, Shi-Yu Huang
2008 J jnl
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.
IEEE Des. Test Comput.
Chao-Wen Tzeng, Shi-Yu Huang
2007 J jnl
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Wen Tzeng, Shi-Yu Huang
2007 J jnl
Robust paradigm for diagnosing hold-time faults in scan chains.
IET Comput. Digit. Tech.
Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang