Chao-Tsung Huang

72 papers A* 4B 1C 4Misc 6Journal 28Unranked 28
YearRankTypeTitle / Venue / Authors
2026 — conf
Tiamat: A 98-to-134ms/Step Transformer-Based Diffusion Model Processor Supporting Classifier-Free Guidance for Image Generation.
ISSCC
Po-Yen Lu, Po-Wei Chen, Shau-Hua Yeh, Zhi-Jun Zhang, Yong-Tai Chen, Ting-Yu Wang, Chao-Tsung Huang
2025 — conf
2.5 A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos.
ISSCC
Yu-Chun Ding, Chia-Yu Chang, Chun-Yeh Lin, Hui-Yun Tsai, Hao-Jiun Tu, Kai-Feng Chang, Yu-Ching Su, Tsung-Han Hsieh, Yu-Kuan Jian, Wen-Ching Chen, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chao-Tsung Huang
2025 — conf
2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming.
ISSCC
Kai-Ping Lin, Tong Wu, Chang-Pao Lin, Po-Wei Chen, Zhi-Jun Zhang, Win-San Khwa, Meng-Fan Chang, Chao-Tsung Huang
2025 J jnl
Conscious Frontier Analysis Model: Learning-Based Path Planning for PointGoal Navigation.
IEEE Trans Autom. Sci. Eng.
Shri Harish Manoharan, Wei-Yu Chiu, Chao-Tsung Huang
2025 J jnl
Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs.
IEEE Trans. Very Large Scale Integr. Syst.
Yong-Tai Chen, Yen-Ting Chiu, Hao-Jiun Tu, Chao-Tsung Huang
2025 J jnl
High-Fidelity Depth Map Reconstruction System With RGB-Guided Super Resolution CNN and Cross-Calibrated Chaos LiDAR.
IEEE Access
Yu-Chun Ding, Chia-Yu Chang, Pei-Rong Li, Chao-Tsung Huang, Yung-Chen Lin, Tsung Chen, Wei-Lun Lin, Cheng-Ting Lee, Fan-Yi Lin, Yuan-Hao Huang
2025 J jnl
Temporal Fusion: Continuous-Time Light Field Video Factorization.
IEEE Trans. Image Process.
Li-De Chen, Li-Qun Weng, Hao-Chien Cheng, An-Yu Cheng, Chao-Tsung Huang
2025 J jnl
VISTA: A Memory-Efficient CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration.
IEEE J. Solid State Circuits
Kai-Ping Lin, Jia-Han Liu, Hong-Chuan Liao, Jyun-Yi Wu, Tong Wu, Chao-Tsung Huang
2024 — conf
A 16nm 231mW Channel MLP Optimized Neural Processing Unit for 80.3% Top-1 ImageNet Classification Accuracy at 102fps.
A-SSCC
Yong-Tai Chen, Hong-Chuan Liao, Hui-Yun Tsai, Kai-Feng Chang, Chao-Tsung Huang
2024 J jnl
VLSI Design of Light-Field Factorization for Dual-Layer Factored Display.
IEEE Trans. Very Large Scale Integr. Syst.
Li-De Chen, Li-Qun Weng, Hao-Chien Cheng, An-Yu Cheng, Kai-Ping Lin, Chao-Tsung Huang
2023 — conf
A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN.
APSIPA ASC
Hao-Jiun Tu, Yu-Feng Ou, Yong-Tai Chen, Chao-Tsung Huang
2023 — conf
VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration.
ISSCC
Kai-Ping Lin, Jia-Han Liu, Jyun-Yi Wu, Hong-Chuan Liao, Chao-Tsung Huang
2022 — conf
A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps.
ESSCIRC
Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang
2022 — conf
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display.
ISSCC
Li-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang
2022 — conf
A Winograd-Based Highly-Parallel Convolution Engine for 8-bit CNN Acceleration.
AICAS
Yong-Tai Chen, Yu-Feng Ou, Chao-Tsung Huang
2022 J jnl
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ching-Te Chiu, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, Yuan-Hao Huang
2021 — conf
A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration.
AICAS
Chi-Wen Weng, Chao-Tsung Huang
2021 — conf
Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer.
SiPS
Hsiu-Pin Hsu, Chao-Tsung Huang
2021 J jnl
Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, Hsueh-Kai Kuo
2021 A* conf
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging.
ISCA
Chao-Tsung Huang
2021 J jnl
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging.
CoRR
Chao-Tsung Huang
2020 Misc conf
Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference.
ICASSP
Chao-Tsung Huang
2020 Misc conf
FIR Filter Design and Implementation for Phase-Based Processing.
ICASSP
Shih-Yao Huang, Wei-Chih Chen, Chao-Tsung Huang
2020 Misc conf
Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition.
ICASSP
Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang
2019 — conf
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications.
VLSI Circuits
Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang
2019 J jnl
ERNet Family: Hardware-Oriented CNN Models for Computational Imaging Using Block-Based Inference.
CoRR
Chao-Tsung Huang
2019 J jnl
Empirical Bayesian Light-Field Stereo Matching by Robust Pseudo Random Field Modeling.
IEEE Trans. Pattern Anal. Mach. Intell.
Chao-Tsung Huang
2019 Misc conf
System and VLSI Implementation of Phase-based View Synthesis.
ICASSP
Han-Chih Huang, Yu-Chih Wang, Wei-Chih Chen, Ping-Yen Lin, Chao-Tsung Huang
2019 A* conf
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference.
MICRO
Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen
2019 J jnl
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference.
CoRR
Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen
2018 Misc conf
A 320M Pixel/S Vlsi Architecture Design of Weighted Mode Filter for 4K Ultra-Hd Depth Upsampling.
ICASSP
Bo-Hsiang Yang, Li-De Chen, Chao-Tsung Huang
2018 — conf
A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA.
A-SSCC
Li-De Chen, Yu-Ta Lu, Yu-Ling Hsiao, Bo-Hsiang Yang, Wei-Chi Chen, Chao-Tsung Huang
2017 J jnl
Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation.
IEEE Trans. Image Process.
Chao-Tsung Huang, Yu-Wen Wang, Li-Ren Huang, Jui Chin, Liang-Gee Chen
2017 A* conf
Robust Pseudo Random Fields for Light-Field Stereo Matching.
ICCV
Chao-Tsung Huang
2016 J jnl
Fast Distribution Fitting for Parameter Estimation of Range-Weighted Neighborhood Filters.
IEEE Signal Process. Lett.
Chao-Tsung Huang
2016 C conf
Fast realistic block-based refocusing for sparse light fields.
ISCAS
Li-Ren Huang, Yu-Wen Wang, Chao-Tsung Huang
2016 C conf
VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps.
ISCAS
Li-De Chen, Yu-Ling Hsiao, Chao-Tsung Huang
2015 — conf
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications.
ISSCC
Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen
2015 J jnl
Bayesian Inference for Neighborhood Filters With Application in Denoising.
IEEE Trans. Image Process.
Chao-Tsung Huang
2015 A* conf
Bayesian inference for neighborhood filters with application in denoising.
CVPR
Chao-Tsung Huang
2015 Misc conf
Fast realistic refocusing for sparse light fields.
ICASSP
Chao-Tsung Huang, Jui Chin, Hong-Hui Chen, Yu-Wen Wang, Liang-Gee Chen
2015 — conf
Sub-pixel disparity estimation in continuous space.
ICCE-TW
Li-De Chen, Jo-Jiun Yu, Wei-Han Cheng, Chao-Tsung Huang
2014 J jnl
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications.
IEEE J. Solid State Circuits
Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan
2014 — ch.
Decoder Hardware Architecture for HEVC.
High Efficiency Video Coding
Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan
2014 B conf
Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization.
ICIP
Mehul Tikekar, Chao-Tsung Huang, Vivienne Sze, Anantha P. Chandrakasan
2014 J jnl
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Tsung Huang, Mehul Tikekar, Anantha P. Chandrakasan
2013 — conf
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications.
ISSCC
Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan
2013 C conf
HEVC interpolation filter architecture for quad full HD decoding.
VCIP
Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan
2007 J jnl
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen
2006 J jnl
High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization.
IEEE Trans. Multim.
Hung-Chi Fang, Yu-Wei Chang, Tu-Chih Wang, Chao-Tsung Huang, Liang-Gee Chen
2006 J jnl
Level C+ data reuse scheme for motion estimation with corresponding coding orders.
IEEE Trans. Circuits Syst. Video Technol.
Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Liang-Gee Chen
2006 — conf
Line Buffer Wordlength Analysis for Line-Based 2-D DWT.
ICASSP (3)
Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen
2006 J jnl
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering.
IEEE Trans. Signal Process.
Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Shao-Yi Chien, Liang-Gee Chen
2005 J jnl
Advances in Hardware Architectures for Image and Video Coding - A Survey.
Proc. IEEE
Po-Chih Tseng, Yung-Chi Chang, Yu-Wen Huang, Hung-Chi Fang, Chao-Tsung Huang, Liang-Gee Chen
2005 J jnl
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Trans. Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 J jnl
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Technol.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 — conf
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications].
ICASSP (5)
Chao-Tsung Huang, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen
2005 — conf
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5)
Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
2005 J jnl
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
J. VLSI Signal Process.
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2005 — conf
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
ISCAS (2)
Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen
2005 — conf
System analysis of VLSI architecture for motion-compensated temporal filtering.
ICIP (3)
Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Chung-Jr Lian, Liang-Gee Chen
2005 J jnl
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
J. VLSI Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 J jnl
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
J. VLSI Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
B-spline factorization-based architecture for inverse discrete wavelet transform.
ISCAS (2)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 J jnl
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
IEEE Trans. Signal Process.
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
Memory analysis and architecture for two-dimensional discrete wavelet transform.
ICASSP (5)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2004 — conf
Reconfigurable discrete cosine transform processor for object-based video signal processing.
ISCAS (2)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2003 — conf
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
ICIP (2)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
ISCAS (5)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
APCCAS (1)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2002 — conf
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
APCCAS (1)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
2002 C conf
VLSI implementation of shape-adaptive discrete wavelet transform.
VCIP
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen