Chao-Chang Chiu

14 papers C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2018 — conf
94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone.
ISSCC
Wei-Chung Chen, Tzu-Chi Huang, Chao-Chang Chiu, Chih-Wei Chang, Kuo-Chun Hsu
2017 J jnl
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shang-Hsien Yang, Tsung-Hsun Tsai, Hsin Chen, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
2016 J jnl
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction.
IEEE Trans. Ind. Electron.
Shang-Hsien Yang, Che-Hao Meng, Chao-Chang Chiu, Chih-Wei Chang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2015 — conf
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
ESSCIRC
Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo
2015 J jnl
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao-Chang Chiu, Po-Hsien Huang, Moris Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee
2014 — conf
A compact power management for next generation intensive care unit with 91% conversion efficiency.
ICCE-TW
Chao-Chang Chiu, Hsiang-An Yang, Yi-Ping Su, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen
2014 J jnl
Self-Calibrated Knee Voltage Detector With 99.65% High Accuracy for AC Charger System in 0.5 µm 500 V UHV Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao-Chang Chiu, Moris Lin, Chih-Wei Chang, Che-Hao Meng, Hsiang-An Yang, Ke-Horng Chen
2013 J jnl
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.
IEEE J. Solid State Circuits
Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee
2013 C conf
Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter.
ISCAS
Moris Lin, Yung-Sheng Huang, Andreas Ehrhart, Yu-Huei Lee, Chao-Chang Chiu, Bernhard Wicht, Ke-Horng Chen
2013 J jnl
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings.
IEEE J. Solid State Circuits
Shen-Yu Peng, Tzu-Chi Huang, Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Tsung-Yen Tsai, Chen-Chih Huang, Long-Der Chen, Cheng-Chen Yang
2012 — conf
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
VLSIC
Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee
2012 J jnl
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System.
IEEE J. Solid State Circuits
Yu-Huei Lee, Chao-Chang Chiu, Shen-Yu Peng, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai
2012 — conf
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.
ESSCIRC
Yu-Huei Lee, Tzu-Chi Huang, Kuan-Yu Chu, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee
2011 — conf
On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system.
A-SSCC
Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Chen-Chih Huang