Changsik Yoo - RankMe

70 papers C 1Journal 49Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	15.10 A Vertical-Cell-Transistor-Based 4F ISSCC Hyunchul Yoon, Youngseok Park, Tae Jin Park, Suk Lae Kim, Seungjae Jung, Daesun Kim, Kyunghwan Kim, Yongjun Kim, Kyuchang Kang, Bokyeon Won, Sang-Hoon Jung, Seunghan Woo, DongGeon Kim, Jonghyuk Kim, In Jung, Junsoo Kim, Jae-Joon Song, Incheol Nam, Young-Hun Seo, Sungsoo Yim, Jemin Park, Changsik Yoo, Sangjoon Hwang
2026	—	`conf`	A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme. ISSCC Kiheung Kim, Hong-Joo Song, Youngdo Um, Jinhun Jang, Seungjun Lee, Ho-Seok Seol, Hye-Jung Kwon, Ji-Hwan Seol, Hoon Shin, Jaehyung Lee, JongMoon Choi, Sung-Woo Yoon, Sang Yun Kim, Dongkeon Lee, Minsoo Jang, Daehyun Kwon, Sangyong Lee, Jinguk Kim, Jonghyuk Kim, In Jung, Taeha Song, Chang Won Kim, Seung Ho Baek, Jinyong Choi, Young-Hun Seo, Won Ho Choi, Changsik Yoo, Sangjoon Hwang
2025	J	`jnl`	A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. IEEE J. Solid State Circuits Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Changsik Yoo, Tae-Young Oh, Sangjoon Hwang
2025	J	`jnl`	A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM. IEEE Solid State Circuits Lett. Changyoung Lee, Youngseok Park, Hyunchul Yoon, Seryeong Yoon, DongGeon Kim, Bokyeon Won, Junhwa Song, Injae Bae, Jae-Joon Song, Kyuchang Kang, Jaehyuk Kim, Kyungrak Cho, Incheol Nam, Jungdon Ihm, Younghun Seo, Changsik Yoo, Sangjun Hwang
2025	J	`jnl`	An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. IEEE J. Solid State Circuits Kyeongtae Nam, Dongil Lee, Kyuchang Kang, Sangyun Kim, Changyoung Lee, Hyunchul Yoon, DongGeon Kim, Bokyeon Won, Jae-Joon Song, Jaehyuk Kim, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang
2025	—	`conf`	Improvement of IGZO BTI for DRAM Cell application by heat treatment and recovery effect. IRPS Changsik Kim, Jongmoo Lee, Jihee Jun, Chanhee Han, In-Jae Bae, Youngkwan Park, Hana Cho, Hyeontae Kim, Dongsik Park, Heonjun Ha, Jae-Joon Song, Changsik Yoo, Sangjoon Hwang
2024	—	`conf`	13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, Youngseok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Taehoon Park, Tae-Young Oh, Changsik Yoo, Sangjoon Hwang
2024	J	`jnl`	A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. IEEE J. Solid State Circuits Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko
2024	—	`conf`	A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. A-SSCC Changyoung Lee, Youngseok Park, Hyunchul Yoon, Seryeong Yoon, DongGeon Kim, Bokyeon Won, Junhwa Song, Injae Bae, Jae-Joon Song, Kyuchang Kang, Jaehyuk Kim, Kyungrak Cho, Incheol Nam, Jungdon Ihm, Younghun Seo, Changsik Yoo, Sangjun Hwang
2024	—	`conf`	An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. VLSI Technology and Circuits Kyeongtae Nam, Jaehyuk Kim, Dongil Lee, Kyuchang Kang, Sangyun Kim, Changyoung Lee, Hyunchul Yoon, DongGeon Kim, Bokyeon Won, Jaejoon Song, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang
2023	—	`conf`	A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh
2023	—	`conf`	A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ISSCC Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, Junhyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee
2023	J	`jnl`	A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han
2023	J	`jnl`	A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han
2023	—	`conf`	A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. A-SSCC Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko
2023	J	`jnl`	An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han
2023	J	`jnl`	DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. CoRR Seungki Hong, Dongha Kim, Jaehyung Lee, Reum Oh, Changsik Yoo, Sangjoon Hwang, Jooyoung Lee
2022	—	`conf`	A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC Dae-Hyun Kim, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee
2021	—	`conf`	A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. ESSCIRC Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee
2021	—	`conf`	A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. VLSI Circuits Seunghwan Hong, Chang-Hyun Bae, Yoo-Chang Sung, Jaewoong Kim, Junsub Yoon, Sangwoo Kim, Jin-Hyeok Baek, Cheongryong Cho, Useung Shin, Sang-Kyeom Kim, Hwan-Chul Jung, Ho-Jun Chang, Jang-Hoo Kim, Jeongsik Hwang, Hyunki Kim, Ki-Won Lee, Dongmin Kim, Han-Ki Jeong, Myung-O. Kim, Kyomin Sohn, Jeong-Don Ihm, Changsik Yoo, Sang Joon Hwang
2021	J	`jnl`	Solar Energy-Harvesting Buck-Boost Converter With Battery-Charging and Battery-Assisted Modes. IEEE Trans. Ind. Electron. Jeongpyo Park, Min-Gyu Jeong, Jin-Gyu Kang, Changsik Yoo
2020	J	`jnl`	A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Hyochang Kim, Changsik Yoo
2020	J	`jnl`	Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter. IEEE Trans. Circuits Syst. II Express Briefs Kyungmin Kim, Changsik Yoo
2019	J	`jnl`	A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator. IEEE Trans. Circuits Syst. II Express Briefs Donghyeok Jeong, Changsik Yoo
2019	J	`jnl`	A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor. IEEE Trans. Ind. Electron. Min-Gyu Jeong, Jin-Gyu Kang, Jeongpyo Park, Changsik Yoo
2019	J	`jnl`	A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range. IEEE J. Solid State Circuits Jin-Gyu Kang, Jeongpyo Park, Min-Gyu Jeong, Changsik Yoo
2019	—	`conf`	Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response. A-SSCC Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo
2018	—	`conf`	A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle. ISSCC Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo
2018	J	`jnl`	Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation. Int. J. Circuit Theory Appl. Baek-Jin Lim, Changsik Yoo
2017	J	`jnl`	A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping. IEEE Access Min-Ki Jeon, Won-Jun Yoo, Chan-Gyu Kim, Changsik Yoo
2017	J	`jnl`	A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. Min-Ki Jeon, Changsik Yoo
2017	J	`jnl`	Duty-cycle and phase spacing error correction circuit for high-speed serial link. IEICE Electron. Express Hyochang Kim, Ook Kim, Changsik Yoo
2016	C	`conf`	A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. ICCE Hyochang Kim, Jaewoo Park, Woosang Han, Kyuhwan Oh, Taekjun Ahn, Jun-Gi Jo, Ook Kim, Changsik Yoo
2016	J	`jnl`	Quasi-Resonant (QR) Controller With Adaptive Switching Frequency Reduction Scheme for Flyback Converter. IEEE Trans. Ind. Electron. Jeongpyo Park, Young-Jin Moon, Min-Gyu Jeong, Jin-Gyu Kang, Sang-hyun Kim, Jung-Chul Gong, Changsik Yoo
2016	J	`jnl`	Wireless power charger for wearable medical devices with in-band communication. Int. J. Circuit Theory Appl. Young-Jin Moon, Jeongpyo Park, Min-Gyu Jeong, Sang-hyun Kim, Jin-Gyu Kang, Dong-Zo Kim, Changsik Yoo
2015	J	`jnl`	A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process. Int. J. Circuit Theory Appl. Keun-Seon Ahn, Jaewoo Park, Changsik Yoo
2015	J	`jnl`	A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process. Int. J. Circuit Theory Appl. Keun-Seon Ahn, Changsik Yoo
2015	J	`jnl`	A switch-mode boost DC-DC converter for IR-drop compensation of charging cable. Int. J. Circuit Theory Appl. Young-Jin Moon, Changsik Yoo
2015	J	`jnl`	An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier. IEICE Electron. Express Jinho Noh, Jisoo Lee, Changsik Yoo
2015	J	`jnl`	Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface. Int. J. Circuit Theory Appl. Younghoon Kim, Changsik Yoo
2015	J	`jnl`	Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM. IEEE Trans. Circuits Syst. II Express Briefs Kyungmin Kim, Changsik Yoo
2014	J	`jnl`	A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop. IEICE Electron. Express Dong-Ho Choi, Changsik Yoo
2014	J	`jnl`	A 100-kS/s 8.3-ENOB 1.7- µW Time-Domain Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs Younghoon Kim, Changsik Yoo
2014	J	`jnl`	A fast automatic frequency calibration technique for a 2-6 GHz frequency synthesizer. Int. J. Circuit Theory Appl. Chan-Young Jeong, Dong-Ho Choi, Changsik Yoo
2014	J	`jnl`	Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples. IEICE Electron. Express Chang-Hyun Bae, Changsik Yoo
2014	—	`conf`	Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control. ISIC Younghoon Kim, Min-Ki Jeon, Changsik Yoo
2013	J	`jnl`	A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid. IEEE J. Solid State Circuits Jinho Noh, Dongjun Lee, Jun-Gi Jo, Changsik Yoo
2013	J	`jnl`	Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. IEEE Trans. Very Large Scale Integr. Syst. Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo
2012	J	`jnl`	Load-Independent Current Control Technique of a Single-Inductor Multiple-Output Switching DC-DC converter. IEEE Trans. Circuits Syst. II Express Briefs Young-Jin Moon, Yong-Seong Roh, Jung-Chul Gong, Changsik Yoo
2012	J	`jnl`	Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization. IEEE Trans. Circuits Syst. II Express Briefs Jang-Woo Lee, Chang-Hyun Bae, Younghoon Kim, Changsik Yoo
2011	J	`jnl`	A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA. IEEE J. Solid State Circuits Jun-Gi Jo, Jinho Noh, Changsik Yoo
2011	J	`jnl`	A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications. IEEE J. Solid State Circuits Kyoohyun Lim, Sunki Min, Sang-Hoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun
2010	J	`jnl`	A 0.6 V, 2.11 MHz, 62 dB SFDR active-RC filter in 0.13µm CMOS process. Int. J. Circuit Theory Appl. Ji-Hwan Seok, Jun-Gi Jo, Changsik Yoo
2010	J	`jnl`	A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport. IEEE Trans. Consumer Electron. Kyungyoul Min, Changsik Yoo
2010	—	`conf`	A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications. ESSCIRC Kyoohyun Lim, Sunki Min, Sanghoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun
2010	J	`jnl`	Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices. IEEE Trans. Consumer Electron. Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo
2009	J	`jnl`	A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong
2007	J	`jnl`	Display System Interface without Line Memory for Low-Cost System-on-Glass. IEEE Trans. Consumer Electron. Kyungyoul Min, Changsik Yoo
2005	—	`conf`	A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology. CICC Jun-Gi Jo, Changsik Yoo, Chun-Seok Jeong, Chan-Young Jeong, Mi-Young Lee, Jong-Kee Kwon
2005	J	`jnl`	A low-ripple poly-Si TFT charge pump for driver-integrated LCD panel. IEEE Trans. Consumer Electron. Changsik Yoo, Kyun-Lyeol Lee
2005	—	`conf`	Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio. ISCAS (5) Jin-Hong Hwang, Mi-Young Lee, Chan-Young Jeong, Changsik Yoo
2004	J	`jnl`	A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. IEEE J. Solid State Circuits Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim
2004	—	`conf`	Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. ESSCIRC Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih
2002	J	`jnl`	A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sungkyung Park, Changsik Yoo, Sin-Chong Park
2001	J	`jnl`	A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS. IEEE J. Solid State Circuits Changsik Yoo, Qiuting Huang
1999	J	`jnl`	A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE J. Solid State Circuits Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho
1999	J	`jnl`	A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. IEEE Trans. Consumer Electron. Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim
1998	J	`jnl`	A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning. IEEE J. Solid State Circuits Changsik Yoo, Seung-Wook Lee, Wonchan Kim
1998	—	`conf`	A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. ASP-DAC Changsik Yoo, Wonchan Kim
1995	J	`jnl`	A static power saving TTL-to-CMOS input buffer. IEEE J. Solid State Circuits Changsik Yoo, Min-Kyu Kim, Wonchan Kim