Changmin Sim

18 papers Journal 17Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces.
IEEE J. Solid State Circuits
Hwaseok Shin, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Seon-Been Lee, Taehwan Kim, Chulwoo Kim
2026 J jnl
A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Seongcheol Kim, Changmin Sim, Seungwoo Park, Junseob So, Hwaseok Shin, Taewhan Kim, Seon-Been Lee, Chulwoo Kim
2025 — conf
22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer.
ISSCC
Junseob So, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Seonbeen Lee, Taehwan Kim, Chulwoo Kim
2025 J jnl
A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM.
IEEE Trans. Circuits Syst. II Express Briefs
Taehwan Kim, Changmin Sim, Seungwoo Park, Jinwoo Park, Seongcheol Kim, Hwaseok Shin, Junseob So, Seonbeen Lee, Youngwook Kwon, Chulwoo Kim
2025 J jnl
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces.
IEEE Trans. Very Large Scale Integr. Syst.
Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim
2025 J jnl
A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation.
IEEE Solid State Circuits Lett.
Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim
2025 J jnl
A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jincheol Sim, Changmin Sim, Jonghyuck Choi, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2025 J jnl
A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications.
IEEE J. Solid State Circuits
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling.
IEEE Trans. Circuits Syst. II Express Briefs
Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces.
IEEE J. Solid State Circuits
Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seonbeen Lee, Chulwoo Kim
2024 J jnl
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances.
IEEE J. Solid State Circuits
Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim
2024 J jnl
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024 J jnl
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoonjae Choi, Changmin Sim, Jonghyuck Choi, Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.
IEEE J. Solid State Circuits
Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024 J jnl
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques.
IEEE J. Solid State Circuits
Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim
2024 J jnl
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits
Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim
2023 J jnl
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2023 J jnl
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim