Changhao Yan

100 papers A* 17A 22B 2C 4Journal 40Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinyi Shen, Zihao Chen, Ji Zhuang, Jiangli Huang, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2026 J jnl
High-Dimensional Yield Optimization for Analog Circuits via Monte Carlo Tree Search and Self-Regressive Auto-Encoder Promoted Subspace Decomposed Gaussian Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaoting Chen, Jianping Guo, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2026 J jnl
Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization.
ACM Trans. Design Autom. Electr. Syst.
Jiangli Huang, Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2026 J jnl
WHUTPlace: performance-driven analytical placement of analog ICs with common centroid constraints.
J. Supercomput.
Tao Su, Yong Zhang, Xianrong Qin, Xiaoyu Liang, Changhao Yan, Ning Xu, Bowen Jia
2025 J jnl
APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuyang Zhao, Tianning Gao, Zheng Wu, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 J jnl
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, Xuan Zeng
2025 A conf
BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation.
ICCAD
Haoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu, Xuan Zeng
2025 A conf
INTO-OA: Interpretable Topology Optimization for Operational Amplifiers.
DATE
Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2025 A conf
LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models.
ICCAD
Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 A* conf
Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration.
DAC
Xuyang Zhao, Yiyang Zhao, Zheng Wu, Tianning Gao, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2025 A* conf
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing.
DAC
Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, Xuan Zeng
2025 A conf
NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction.
ICCAD
Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025 A conf
Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search.
ICCAD
Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2025 J jnl
VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aidong Zhao, Ruiyu Lyu, Xuyang Zhao, Zhaori Bi, Fan Yang, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng
2025 J jnl
pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhixuan Dong, Longlong Yang, Cuiyang Ding, Changhao Yan, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 B conf
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper).
ASPDAC
Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2024 A conf
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
ICCAD
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 J jnl
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
CoRR
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 B conf
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing.
ASPDAC
Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng
2024 J jnl
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng
2024 A conf
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data.
DATE
Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng
2024 J jnl
D
ACM Trans. Design Autom. Electr. Syst.
Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Walter Hu, Dian Zhou
2024 A* conf
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration.
DAC
Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 A conf
Exploring High-dimensional Search Space via Voronoi Graph Traversing.
UAI
Aidong Zhao, Xuyang Zhao, Tianchen Gu, Zhaori Bi, Xinwei Sun, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2024 A* conf
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing.
DAC
Tianchen Gu, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng
2024 J jnl
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuyang Zhao, Tianning Gao, Aidong Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2024 A conf
Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis.
ICCAD
Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2024 J jnl
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2024 A conf
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling.
DATE
Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng
2023 J jnl
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi, Xuan Zeng
2023 J jnl
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography.
J. Comput. Phys.
Cuiyang Ding, Yijing Zhou, Wei Cai, Xuan Zeng, Changhao Yan
2023 J jnl
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiangli Huang, Chuyu Wang, Yuyang Yan, Cong Tao, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2023 A* conf
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
DAC
Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
2022 C conf
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
ISCAS
Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng
2022 A conf
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions.
ICCAD
Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng
2022 — conf
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
ASP-DAC
Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou
2022 J jnl
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions.
SIAM J. Sci. Comput.
Cuiyang Ding, Changhao Yan, Xuan Zeng, Wei Cai
2022 J jnl
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2022 A* conf
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
DAC
Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2022 J jnl
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng
2022 — conf
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
MLCAD
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2022 C conf
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing.
ISCAS
Hao Jiang, Fan Yang, Changhao Yan, Xuan Zeng
2021 — conf
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits.
ASICON
Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng
2021 J jnl
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2021 — conf
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
ASP-DAC
Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 J jnl
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A conf
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.
DATE
Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2021 A* conf
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization.
DAC
Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng
2021 C conf
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
ISCAS
Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 — conf
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling.
ASICON
Yingqi Li, Fan Yang, Changhao Yan, Xuan Zeng
2021 — conf
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure.
ASICON
Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 J jnl
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
CoRR
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021 A* conf
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
DAC
Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng
2020 A conf
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
DATE
Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2020 A* conf
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
DAC
Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2019 A conf
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
DATE
Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2019 A* conf
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
DAC
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
2019 J jnl
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
CoRR
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
2019 A conf
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
DATE
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2019 J jnl
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
CoRR
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2018 A* conf
A general graph based pessimism reduction framework for design optimization of timing closure.
DAC
Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2018 J jnl
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenlong Lyu, Pan Xue, Fan Yang, Changhao Yan, Zhiliang Hong, Xuan Zeng, Dian Zhou
2018 J jnl
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.
ACM Trans. Design Autom. Electr. Syst.
Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng
2018 A* conf
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits.
DAC
Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou
2018 A* conf
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
ICML
Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2018 J jnl
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng
2018 A* conf
Multi-objective bayesian optimization for analog/RF circuit synthesis.
DAC
Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2018 J jnl
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng
2017 — conf
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.
ISPA/IUCC
Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 J jnl
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst.
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
2017 — conf
An efficient algorithm for stencil planning and optimization in E-beam lithography.
ASP-DAC
Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 A* conf
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits.
DAC
Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu
2017 J jnl
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Mengshuo Wang, Changhao Yan, Xin Li, Dian Zhou, Xuan Zeng
2017 A conf
Impact of circuit-level non-idealities on vision-based autonomous driving systems.
ICCAD
Handi Yu, Changhao Yan, Xuan Zeng, Xin Li
2017 C conf
Layout decomposition for hybrid E-beam and DSA double patterning lithography.
ISCAS
Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu
2017 — conf
Network flow based cut redistribution and insertion for advanced 1D layout design.
ASP-DAC
Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2017 A conf
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
DATE
Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2016 A conf
A novel unified dummy fill insertion framework with SQP-based optimization method.
ICCAD
Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2016 A conf
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
DATE
Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou
2016 J jnl
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng
2015 J jnl
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst.
Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
2015 — conf
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
ASP-DAC
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou
2015 J jnl
Multi-parameter clock skew scheduling.
Integr.
Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng
2015 J jnl
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method.
Integr.
Zhenyu Wu, Changhao Yan, Xuan Zeng, Sheng-Guo Wang
2013 J jnl
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Sci. Comput.
Changhao Yan, Wei Cai, Xuan Zeng
2013 J jnl
An efficient method for gradient-aware dummy fill synthesis.
Integr.
Peng Wu, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2013 A conf
Layout decomposition with pairwise coloring for multiple patterning lithography.
ICCAD
Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng
2013 J jnl
Post-routing layer assignment for double patterning with timing critical paths consideration.
Integr.
Jian Sun, Yinghai Lu, Hai Zhou, Changhao Yan, Xuan Zeng
2012 J jnl
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng
2011 A conf
A new method for multiparameter robust stability distribution analysis of linear analog circuits.
ICCAD
Changhao Yan, Sheng-Guo Wang, Xuan Zeng
2011 A conf
An efficient algorithm for multi-domain clock skew scheduling.
DATE
Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng
2011 J jnl
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2009 J jnl
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2009 A* conf
Provably good and practically efficient algorithms for CMP dummy fill.
DAC
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng
2008 — conf
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
ISQED
Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai
2008 — conf
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
ISQED
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2008 — conf
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
ASP-DAC
Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan
2008 A* conf
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
DAC
Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni
2006 — conf
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
ISQED
Changhao Yan, Wenjian Yu, Zeyi Wang
2006 — conf
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
ASP-DAC
Changhao Yan, Wenjian Yu, Zeyi Wang