Chang Wu - RankMe

51 papers A* 4A 4C 4Misc 2Journal 21Unranked 16

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	CRAB-EDM: A Multi-Modal Underwater Crab-Inspired Robot With Temporally Sequenced Electro-Discharge Modulation. IEEE Robotics Autom. Lett. Xia Huang, Haomin Xiang, Chang Wu, Jiabin Xu, Jun Ding, Yanhong Peng, Yuki Funabora
2026	J	`jnl`	Design space exploration for layer-specific efficiency enhancement in CNN accelerators. Array Mengxuan Wang, Chang Wu
2026	J	`jnl`	Kaiwu-PyTorch-Plugin: Bridging Deep Learning and Photonic Quantum Computing for Energy-Based Models and Active Sample Selection. CoRR Hongdong Zhu, Qi Gao, Yin Ma, Shaobo Chen, Haixu Liu, Feng-ao Wang, Tinglan Wang, Chang Wu, Kai Wen
2026	J	`jnl`	Multi-View Manifold-Adaptive Kernel Regression for Speech Classification From EEG Signals. IEEE Signal Process. Lett. Xie He, Qi Cui, Chang Wu, Yong Peng, Wanzeng Kong
2026	J	`jnl`	Prototype Distance and Local Manifold Guided Sample-Weighted Kernel Clustering. IEEE Signal Process. Lett. Chang Wu, Pengxin Xu, Zhaohu Liu, Luyun Wang, Yong Peng
2025	J	`jnl`	A lightweight frame buffer compression codec for memory-efficient applications. Microelectron. J. Zekun Zhang, Chang Wu
2025	J	`jnl`	CFP: Low-overhead Profiling-based Intra-operator Parallelism Generation by Preserving Communication-Free Structures. CoRR Weifang Hu, Xuanhua Shi, Chang Wu, Yunkai Zhang, Xuan Peng, Jiaqi Zhai, Hai Jin, Yongluan Zhou, Xuehai Qian
2025	J	`jnl`	Integrated STL-DBSCAN algorithm for online hydrological and water quality monitoring data cleaning. Environ. Model. Softw. Chenyu Song, Jingyuan Cui, Yafei Cui, Sheng Zhang, Chang Wu, Xiaoyan Qin, Qiaofeng Wu, Shanqing Chi, Mingqing Yang, Jia Liu, Ruihong Chen, Haiping Zhang
2025	J	`jnl`	L3former: Enhanced multi-scale shared Transformer with Local Linear Layer for long-term series forecasting. Inf. Fusion Yulin Xia, Chang Wu, Xiaoman Yang
2025	J	`jnl`	Radical or Incremental? The Effects of Green Innovation on the Supply Base Stability of Logistics Service Providers. IEEE Trans. Engineering Management Chang Wu, Jinan Shao, Kee-Hung Lai, Yongyi Shou
2024	J	`jnl`	Compact Tunable Reflectionless Phase Shifter With Wide Bandwidth and Low Phase Deviation. IEEE Trans. Circuits Syst. II Express Briefs Zilan Cao, Xiaojun Bi, Andy Shen, Chang Wu, Zhen Huang, Tao Guo, Qinfen Xu
2024	Misc	`conf`	NetAssistant: Dialogue Based Network Diagnosis in Data Center Networks. NSDI Haopei Wang, Anubhavnidhi Abhashkumar, Changyu Lin, Tianrong Zhang, Xiaoming Gu, Ning Ma, Chang Wu, Songlin Liu, Wei Zhou, Yongbin Dong, Weirong Jiang, Yi Wang
2023	—	`conf`	A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation. ASICON Mengxuan Wang, Yuan Linghu, Chang Wu
2023	C	`conf`	A Model-driven Early Warning Approach for Transmission Lines Failure under Wind Storms. iSPEC Haoran Chen, Shibin Bai, Zhihao Tian, Gang Liu, Changgang Li, Qiulong Ni, Chang Wu
2023	—	`conf`	An Efficient Scheduling Algorithm for Stream Computing. ASICON Kexin Wang, Jundong Xie, Yiwei Wang, Chang Wu
2023	J	`jnl`	Dual-Band Power Divider With Wide Passbands and Wide Harmonic Suppression Utilizing Multi-Mode T-Stub Loaded Slotline Resonators. IEEE Trans. Circuits Syst. II Express Briefs Zhe Zhang, Xiaojun Bi, Qiang Ma, Andy Shen, Chang Wu, Tao Guo, Qinfen Xu
2023	—	`conf`	HierSyn: Fast Synthesis for Large Hierarchical Designs. ASICON Yishan Zhang, Zhiyong Zhang, Chang Wu
2023	—	`conf`	Millimeter-Wave AlGaN/GaN MIS-HEMTs with Multiple T-Gate Technology. ICTA Jielong Liu, Chang Wu, Tao Guo, Kai Wang, Chengcheng Li, An Liu, Rui Zhou, Zhen Huang, Jiayan Wu, Minhan Mi, Xiaohua Ma
2022	C	`conf`	Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results. ISCAS Luchang Ding, Chang Cai, Gengsheng Chen, Zehao Wu, Jing Zhang, Chang Wu, Jun Yu
2022	—	`conf`	Collar Data Synthesis and Its Application for Generating Virtual Collar 3D Novel View from a Single-View. ISPA/BDCloud/SocialCom/SustainCom Na Guo, Pei-Wei Tsai, Hongwang Xiao, Chang Wu, Wenjuan Duan
2022	—	`conf`	Hybrid video coding scheme based on VVC and spatio-temporal attention convolution neural network. CVPR Workshops Gang He, Kepeng Xu, Chang Wu, Zijia Ma, Xing Wen, Ming Sun
2022	C	`conf`	Real-Time Image Inpainting using PatchMatch Based Two-Generator Adversarial Networks with Optimized Edge Loss Function. ISCAS Luchang Ding, Jing Zhang, Chang Wu, Chang Cai, Gengsheng Chen
2021	J	`jnl`	Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism. ACM Trans. Reconfigurable Technol. Syst. Zhenghua Gu, Wenqin Wan, Jundong Xie, Chang Wu
2021	—	`conf`	Highly Efficient Modulo Loop Pipeline For High Level Synthesis. ASICON Chang Wu, Jundong Xie, Kexin Wang
2020	J	`jnl`	Qualitative analysis of intellectual property forgery in manufacturing enterprises in Industry 4.0 environment. Int. J. Technol. Manag. Chang Wu
2019	A	`conf`	A Reconfigurable Accelerator for Sparse Convolutional Neural Networks. FPGA Weijie You, Chang Wu
2019	—	`conf`	An Efficient Accelerator for Sparse Convolutional Neural Networks. ASICON Weijie You, Chang Wu
2019	J	`jnl`	Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits. IEICE Electron. Express Liewei Xu, Chang Cai, Tianqi Liu, Lingyun Ke, Jun Yu, Chang Wu
2019	A	`conf`	Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions. FPGA Yanjie Gu, Jian Yu, Tieli Sun, Chen Pan, Zhenhao Feng, Liewei Xu, Chang Wu
2019	—	`conf`	Latency Minimal Scheduling with Maximum Instruction Parallelism. ASICON Zhenghua Gu, Wenqin Wan, Chang Wu
2018	—	`conf`	Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. SLIP@DAC Xinheng Liu, Dae Hee Kim, Chang Wu, Deming Chen
2017	—	`conf`	Heterogeneous computing for CNN. ASICON Huizi Zhang, Chang Wu, Xiao Hu
2017	J	`jnl`	Layout driven FPGA packing algorithm for performance optimization. IEICE Electron. Express Linfeng Mo, Chang Wu, Lei He, Gengsheng Chen
2016	—	`conf`	In-place LUT polarity inVersion to mitigate soft errors for FPGAs. DFT Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He
2015	A	`conf`	Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
2014	J	`jnl`	A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip. J. Comput. Song Chai, Yubai Li, Jian Wang, Chang Wu
2014	—	`conf`	Providing Useful Information for Passengers Based on TTF Model. iThings/GreenCom/CPSCom Yangdong Liu, Ye Tian, Bo Yuan, Chang Wu, Weishuo Qian, Wei Mao
2013	Misc	`conf`	The implementation of an improve infrared dim-small target track before detect based on DSP. ICMLC Qingbo Ji, Chao Ren, Lewei Qu, Chang Wu
2011	J	`jnl`	An analytical model for Network-on-Chip with finite input buffer. Frontiers Comput. Sci. China Jian Wang, Yubai Li, Chang Wu
2009	J	`jnl`	Shortest path based simulated annealing algorithm for dynamic facility layout problem under dynamic business environment. Expert Syst. Appl. Ming Dong, Chang Wu, Forest Hou
2008	—	`conf`	A NoC Simulation and Verification Platform Based on SystemC. CSSE (3) Song Chai, Chang Wu, Yubai Li, Zhongming Yang
2008	—	`conf`	Lottery Router: A Customized Arbitral Priority NOC Router. CSSE (3) Chang Wu, Yubai Li, Song Chai, Zhongming Yang
2002	—	`conf`	Global clustering-based performance-driven circuit partitioning. ISPD Jason Cong, Chang Wu
2000	A*	`conf`	Performance driven multi-level and multiway partitioning with retiming. DAC Jason Cong, Sung Kyu Lim, Chang Wu
1999	A	`conf`	Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA Jason Cong, Chang Wu, Yuzheng Ding
1999	J	`jnl`	Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Chang Wu
1999	A*	`conf`	Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. DAC Jason Cong, Honching Li, Chang Wu
1998	J	`jnl`	An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Chang Wu
1998	A*	`conf`	Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. DAC Jason Cong, Chang Wu
1997	A*	`conf`	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC Jason Cong, Chang Wu
1996	C	`conf`	An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ICCD Jason Cong, Chang Wu