Chang-Ming Lai

14 papers C 2Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2020 — conf
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS.
ISSCC
Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a
2015 J jnl
A 0.003 mm
IEEE J. Solid State Circuits
Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee
2014 — conf
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.
ISSCC
Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu
2014 J jnl
A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chang-Ming Lai, Kai-Wen Tan, Yen-Ju Chen, Ta-Shun Chu
2014 — conf
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer.
A-SSCC
Chin-Fu Li, Shih-Chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang
2014 — conf
A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.
VLSI-DAT
Cuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang
2013 — conf
A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS.
ISSCC
Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu
2013 — conf
Time-domain analog-to-digital converters with domino delay lines.
VLSI-DAT
Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang
2012 — conf
A UWB IR timed-array radar using time-shifted direct-sampling architecture.
VLSIC
Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
2011 C conf
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
ISCAS
Chang-Ming Lai, Meng-Hung Shen, Yi-Da Wu, Kai-Hsiang Huang, Po-Chiun Huang
2011 — conf
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection.
A-SSCC
Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang
2011 — conf
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
ISOCC
Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang
2010 J jnl
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits
Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, Po-Chiun Huang
2006 C conf
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.
ISCAS
Yi-Da Wu, Chang-Ming Lai, Chih-Yuan Chou, Po-Chiun Huang