Chandramouli Visweswariah

24 papers A* 8A 8Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2006 J jnl
First-Order Incremental Block-Based Statistical Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett
2006 J jnl
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2005 J jnl
Large-scale nonlinear optimization in circuit tuning.
Future Gener. Comput. Syst.
Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn
2004 A* conf
First-order incremental block-based statistical timing analysis.
DAC
Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan
2004 A* conf
Is statistical timing statistically significant?
DAC
Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
2003 A* conf
Statistical timing for parametric yield prediction of digital integrated circuits.
DAC
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2002 A* conf
Uncertainty-aware circuit optimization.
DAC
Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski
2001 — conf
Overview of continuous optimization advances and applications to circuit tuning.
ISPD
Andrew R. Conn, Chandramouli Visweswariah
2000 J jnl
Noise considerations in circuit optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn
1999 A conf
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation.
ICCAD
Chandramouli Visweswariah, Andrew R. Conn
1999 A* conf
Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation.
DAC
Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan
1998 J jnl
JiffyTune: circuit optimization using time-domain sensitivities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu
1998 A conf
Noise considerations in circuit optimization.
ICCAD
Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah
1997 A conf
Circuit optimization via adjoint Lagrangians.
ICCAD
Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu
1997 A conf
Optimization techniques for high-performance digital circuits.
ICCAD
Chandramouli Visweswariah
1996 A conf
Inaccuracies in power estimation during logic synthesis.
ICCAD
Daniel Brand, Chandramouli Visweswariah
1996 A conf
Optimization of custom MOS circuits by transistor sizing.
ICCAD
Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah
1993 A* conf
Incremental Event-Driven Simulation of Digital FET Circuits.
DAC
Chandramouli Visweswariah, Jalal A. Wehbeh
1992 J jnl
M
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen
1991 A* conf
Efficient Simulation of Bipolar Digital ICs.
DAC
Chandramouli Visweswariah, Ronald A. Rohrer
1991 J jnl
Piecewise approximate circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chandramouli Visweswariah, Ronald A. Rohrer
1990 A conf
Incorporation of Inductors in Piecewise Approximate Circuit Simulation.
ICCAD
Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer
1989 A conf
Piecewise approximate circuit simulation.
ICCAD
Chandramouli Visweswariah, Ronald A. Rohrer
1988 A* conf
Model Development and Verification for High Level Analog Blocks.
DAC
Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen