Chandramouli V. Kashyap

33 papers A* 9A 7Journal 10Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. DATE Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. CoRR Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2021	A*	`conf`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. DAC Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2021	J	`jnl`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. CoRR Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2020	A*	`conf`	MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design. DAC Brett Shook, Prateek Bhansali, Chandramouli V. Kashyap, Chirayu Amin, Siddhartha Joshi
2016	J	`jnl`	Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD. IEEE Des. Test Xin Li, Chandramouli V. Kashyap, Chris J. Myers
2010	J	`jnl`	Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2009	A	`conf`	Quantifying robustness metrics in parameterized static timing analysis. ICCAD Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm
2008	A*	`conf`	A "true" electrical cell model for timing, noise, and power grid verification. DAC Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin
2008	A*	`conf`	A framework for block-based timing sensitivity analysis. DAC Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar
2008	—	`conf`	Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
2008	A	`conf`	Silicon feedback to improve frequency of high-performance microprocessors: an overview. ICCAD Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin
2007	A	`conf`	A nonlinear cell macromodel for digital applications. ICCAD Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout
2007	A*	`conf`	Silicon Speedpath Measurement and Feedback into EDA flows. DAC Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout
2006	A*	`conf`	A multi-port current source model for multiple-input switching effects in CMOS library cells. DAC Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
2006	J	`jnl`	Fast Interconnect and Gate Timing Analysis for Performance Optimization. IEEE Trans. Very Large Scale Integr. Syst. Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap
2005	A*	`conf`	A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. DAC Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter
2004	J	`jnl`	A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
2004	J	`jnl`	Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2004	J	`jnl`	Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2004	J	`jnl`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2003	A	`conf`	Block-based Static Timing Analysis with Uncertainty. ICCAD Anirudh Devgan, Chandramouli V. Kashyap
2003	—	`conf`	Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2003	A*	`conf`	Delay and slew metrics using the lognormal distribution. DAC Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2003	—	`conf`	Realizable reduction of RLC circuits using node elimination. ISCAS (3) Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2002	A	`conf`	A delay metric for RC circuits based on the Weibull distribution. ICCAD Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
2002	—	`conf`	PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2002	—	`conf`	Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2002	—	`conf`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2001	J	`jnl`	RC delay metrics for performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2000	A*	`conf`	A realizable driving point model for on-chip interconnect with inductance. DAC Chandramouli V. Kashyap, Byron Krauter
2000	—	`conf`	A two moment RC delay metric for performance optimization. ISPD Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2000	A	`conf`	An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan