Chandan Kumar Sarkar

52 papers A 1C 1Misc 1Journal 46Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
Introduction to the special section on State-of-the-art Micro-Nano devices and systems.
Comput. Electr. Eng.
Angsuman Sarkar, Chandan Kumar Sarkar, Arezki Benfdila
2020 J jnl
Split gated silicon nanotube FET for bio-sensing applications.
IET Circuits Devices Syst.
Avtar Singh, Saurabh Chaudhury, Manash Chanda, Chandan Kumar Sarkar
2019 J jnl
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.
IET Circuits Devices Syst.
Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose
2019 J jnl
Design and analysis of high
IET Circuits Devices Syst.
Avtar Singh, Saurabh Chaudhury, Chandan Kumar Pandey, Savitesh Madhulika Sharma, Chandan Kumar Sarkar
2019 J jnl
Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures.
Microelectron. J.
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
2018 J jnl
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing.
IET Circuits Devices Syst.
Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar
2018 J jnl
Development of integrated microsystem for hydrogen gas detection.
IET Circuits Devices Syst.
Swapan Das, Chandan Kumar Sarkar, Sunipa Roy
2018 J jnl
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET.
IEEE Trans. Circuits Syst. II Express Briefs
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar
2017 J jnl
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application.
J. Low Power Electron.
Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar
2017 J jnl
Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs.
IET Circuits Devices Syst.
Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar
2016 J jnl
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET.
ACM J. Emerg. Technol. Comput. Syst.
Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar
2016 J jnl
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET.
Microelectron. Reliab.
Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan Kumar Sarkar
2016 J jnl
Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.
Microelectron. Reliab.
Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar
2016 J jnl
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor.
IET Circuits Devices Syst.
Sagar Mukherjee, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
2016 J jnl
Study of process induced variability of germanium-pTFET in analog and RF domain.
Microelectron. Reliab.
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
2016 J jnl
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance.
IET Circuits Devices Syst.
Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar
2015 J jnl
Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications.
J. Low Power Electron.
Atanu Kundu, Arka Dutta, Chandan Kumar Sarkar
2015 J jnl
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application.
J. Circuits Syst. Comput.
Manash Chanda, Swapnadip De, Chandan Kumar Sarkar
2015 J jnl
Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs.
J. Low Power Electron.
Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar
2015 J jnl
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET.
Microelectron. J.
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar
2015 J jnl
Impact of the lateral straggle on the Analog and RF performance of TFET.
Microelectron. Reliab.
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
2015 J jnl
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application.
IEEE Trans. Very Large Scale Integr. Syst.
Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar
2014 J jnl
Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer.
Microelectron. Reliab.
Arka Dutta, Kalyan Koley, Chandan Kumar Sarkar
2014 J jnl
Analysis of flicker and thermal noise in p-channel Underlap DG FinFET.
Microelectron. Reliab.
Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar
2014 J jnl
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique.
J. Signal Process. Syst.
D. Kayal, Posiba Mostafa, Anup Dandapat, Chandan Kumar Sarkar
2014 J jnl
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET.
Microelectron. Reliab.
Atanu Kundu, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
2014 J jnl
RF parameter extraction of underlap DG MOSFETs: a look up table based approach.
IET Circuits Devices Syst.
Atanu Kundu, Arka Dutta, Kalyan Koley, S. Niyogi, Chandan Kumar Sarkar
2014 J jnl
Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs.
Microelectron. Reliab.
Sudhansu Kumar Pati, Kalyan Koley, Arka Dutta, N. Mohankumar, Chandan Kumar Sarkar
2013 J jnl
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme.
CoRR
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar
2013 J jnl
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit.
CoRR
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
2013 A conf
Integration of ZnO nanoflakes with MEMS platform and its application as gas sensor.
ICST
Partha Bhattacharyya, Sunipa Roy, Chandan Kumar Sarkar
2012 J jnl
1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model.
IET Circuits Devices Syst.
Angsuman Sarkar, Swapnadip De, Anup Dey, Chandan Kumar Sarkar
2012 — conf
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications.
ISED
Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar
2012 — conf
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme.
ISED
Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
2012 J jnl
Effect of gate engineering in double-gate MOSFETs for analog/RF applications.
Microelectron. J.
Angsuman Sarkar, Aloke Kumar Das, Swapnadip De, Chandan Kumar Sarkar
2012 — conf
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.
VDAT
Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar
2012 J jnl
Modeling of noise for p-channel DG-FinFETs.
Microelectron. Reliab.
Srabanti Pandit, Binit Syamal, Chandan Kumar Sarkar
2012 J jnl
Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions.
Microelectron. Reliab.
Kalyan Koley, Binit Syamal, Atanu Kundu, N. Mohankumar, Chandan Kumar Sarkar
2011 J jnl
Effects of La
Microelectron. Reliab.
D. Zade, Soshi Sato, Kuniyuki Kakushima, A. Srivastava, Parhat Ahmet, Kazuo Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, Chandan Kumar Sarkar, Hiroshi Iwai
2011 Misc conf
Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs.
VLSI Design
Srabanti Pandit, Chandan Kumar Sarkar
2011 J jnl
Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device.
Microelectron. Reliab.
A. Srivastava, R. K. Nahar, Chandan Kumar Sarkar, W. P. Singh, Y. Malhotra
2011 J jnl
Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications.
IET Circuits Devices Syst.
Saurav Chakraborty, Abhijit Mallik, Chandan Kumar Sarkar
2010 J jnl
Electron transport in two dimensional electron gas formed at the heterojunction of Al
Microelectron. Reliab.
Amrita Chakraborty, Chandan Kumar Sarkar
2009 J jnl
Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications.
Microelectron. Reliab.
N. Mohankumar, Binit Syamal, Chandan Kumar Sarkar
2009 J jnl
MIMO Based Multimedia Communication System
CoRR
Debdatta Kandar, Sourav Dhar, Rabindranath Bera, Chandan Kumar Sarkar
2009 J jnl
Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications.
Microelectron. Reliab.
A. Srivastava, Partha Sarkar, Chandan Kumar Sarkar
2009 J jnl
Study on the performance of sub 100 nm LACLATI MOSFETs for digital application.
Microelectron. Reliab.
Partha Sarkar, Abhijit Mallik, Chandan Kumar Sarkar
2008 J jnl
A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain.
Microelectron. Reliab.
Srimanta Baishya, Abhijit Mallik, Chandan Kumar Sarkar
2007 C conf
Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.
VLSI-SoC
Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar
2007 J jnl
Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs.
Microelectron. Reliab.
Partha Sarkar, Abhijit Mallik, Chandan Kumar Sarkar
2007 J jnl
Realization of quantum dot Boolean logic gate for image processing applications.
J. Electronic Imaging
M. Ganguly, Chandan Kumar Sarkar
2006 J jnl
Comparative studies on electronic transport due to the reduced dimensionality at the heterojunctions of GaAs/A1
Microelectron. J.
S. Shrestha, Chandan Kumar Sarkar