Chandan Karfa - RankMe

79 papers A 3C 2Misc 10Journal 36Unranked 27

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis. CoRR Nilotpola Sarma, Vaishali Ghanshyam Chaudhuri, Chandan Karfa
2026	Misc	`conf`	Probabilistic Neural Network Models for RTL Designs. VLSID Hetang Patel, E. Bhawani Eswar Reddy, Chandan Karfa, Samik Das
2026	Misc	`conf`	RTL Information Tracker and its Applications in Quantifying the Security Impact of HLS Optimizations. VLSID Nilotpola Sarma, Sunny Priyadarshi, Chandan Karfa
2026	J	`jnl`	STRAP-ViT: Segregated Tokens with Randomized - Transformations for Defense against Adversarial Patches in ViTs. CoRR Nandish Chattopadhyay, Anadi Goyal, Chandan Karfa, Anupam Chattopadhyay
2026	—	`conf`	Safeguarding Neural Network IPs from Scan Chain based Model Extraction Attacks. ASP-DAC E. Bhawani Eswar Reddy, Gundameedi Sai Ram Mohan, Sukanta Bhattacharjee, Chandan Karfa
2026	—	`ed.`	Security, Privacy, and Applied Cryptography Engineering - 15th International Conference, SPACE 2025, Guwahati, India, December 16-19, 2025, Proceedings SPACE Chandan Karfa, Navid Asadi, Anupam Chattopadhyay
2025	J	`jnl`	David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design? CoRR Shashwat Shankar, Subhranshu Pandey, Innocent Dengkhw Mochahari, Bhabesh Mali, Animesh Basak Chowdhury, Sukanta Bhattacharjee, Chandan Karfa
2025	J	`jnl`	Developing Deadlock-Free Routing Algorithms in Torus NoC: A Formal Approach. ACM Trans. Embed. Comput. Syst. Surajit Das, Abhijit Das, Chandan Karfa
2025	J	`jnl`	Efficient Register-Balancing for Masked Hardware. IEEE Embed. Syst. Lett. Nilotpola Sarma, Sujeet Narayan Kamble, Chandan Karfa
2025	Misc	`conf`	LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models. VLSID Sutirtha Bhattacharyya, Fedrick Nongpoh, Karthik Maddala, E. Bhawani Eswar Reddy, Chandan Karfa
2025	J	`jnl`	LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks. ACM Trans. Design Autom. Electr. Syst. E. Bhawani Eswar Reddy, Sutirtha Bhattacharyya, Ankur Sarmah, Fedrick Nongpoh, Karthik Maddala, Chandan Karfa
2025	J	`jnl`	SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine. CoRR Adarsh Gupta, Bhabesh Mali, Chandan Karfa
2025	J	`jnl`	SHIELD: Security-Aware Scheduling for Real-Time DAGs on Heterogeneous Systems. ACM Trans. Cyber Phys. Syst. Debabrata Senapati, Pooja Bhagat, Chandan Karfa, Arnab Sarkar
2025	Misc	`conf`	TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level. VLSID Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
2024	—	`conf`	ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation. ISVLSI Bhabesh Mali, Karthik Maddala, Vatsal Gupta, Sweeya Reddy, Chandan Karfa, Ramesh Karri
2024	J	`jnl`	ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation. CoRR Bhabesh Mali, Karthik Maddala, Sweeya Reddy, Vatsal Gupta, Chandan Karfa, Ramesh Karri
2024	Misc	`conf`	ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems. VLSID Debabrata Senapati, Dharmendra Maurya, Arnab Sarkar, Chandan Karfa
2024	Misc	`conf`	Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. VLSID Praveen Karmakar, Marpina Bharani, Chandan Karfa
2024	J	`jnl`	LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification. CoRR Karthik Maddala, Bhabesh Mali, Chandan Karfa
2024	A	`conf`	LEAP: Learning guided Quality Cut selection for faster Technology Mapping. ICCAD Chandrabhusan Reddy Chigarapally, Harshwardhan Nitin Bhakkad, Animesh Basak Chowdhury, Chandan Karfa, Sukanta Bhattacharjee
2024	—	`conf`	LLM vs HLS for RTL Code Generation: Friend or Foe? ATS Sutirtha Bhattacharyya, Sutharshanan B. G, Chandan Karfa
2024	J	`jnl`	MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. CoRR Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
2024	J	`jnl`	MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
2024	—	`conf`	NoBALL: A Novel BDD-based Attack against Logic Locking. ITC-Asia Praveen Karmakar, Anmoldeep Singh, Kartik Sharma, Chandan Karfa, Sukanta Bhattacharjee
2024	—	`conf`	RTL Simulation Acceleration with Machine Learning Models. ISQED Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati
2024	Misc	`conf`	SRIL: Securing Registers from Information Leakage at Register Transfer Level. VLSID Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa
2024	—	`conf`	Security Concerns of Machine Learning Hardware. ATS Nilotpola Sarma, E. Bhawani Eswar Reddy, Chandan Karfa
2023	—	`conf`	An Investigation into the Security of Register Allocation with Spilling and Splitting. ISVLSI Priyanka Panigrahi, Chandan Karfa
2023	J	`jnl`	Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debabrata Senapati, Arnab Sarkar, Chandan Karfa
2023	J	`jnl`	TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Design Autom. Electr. Syst. Debabrata Senapati, Kousik Rajesh, Chandan Karfa, Arnab Sarkar
2023	J	`jnl`	Translation Validation of Information Leakage of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Priyanka Panigrahi, Chandan Karfa
2022	J	`jnl`	Accelerating NoC Verification Using a Complete Model and Active Window. IEEE Access Surajit Das, Chandan Karfa, Santosh Biswas
2022	J	`jnl`	Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC. IEEE Embed. Syst. Lett. Surajit Das, Chandan Karfa
2022	J	`jnl`	BLAST: Belling the Black-Hat High-Level Synthesis Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammed Abderehman, Rupak Gupta, Theegala Rakesh Reddy, Chandan Karfa
2022	—	`conf`	Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking. ISQED Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay
2022	—	`conf`	DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis. ISQED Mohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa
2022	J	`jnl`	FastSim: A Fast Simulation Framework for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza, Yom Nigam, T. M. Abdul Khader, Chandan Karfa
2022	—	`conf`	GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking. ACM Great Lakes Symposium on VLSI Gagan Gayari, Chandan Karfa, Prithwijit Guha
2022	C	`conf`	ImageSpec: Efficient High-Level Synthesis of Image Processing Applications. DSD Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa
2022	J	`jnl`	PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms. IEEE Trans. Computers Debabrata Senapati, Arnab Sarkar, Chandan Karfa
2022	Misc	`conf`	Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems. ICDCN Debabrata Senapati, Arnab Sarkar, Chandan Karfa
2022	J	`jnl`	Quantifying Information Leakage for Security Verification of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Priyanka Panigrahi, Abhik Paul, Chandan Karfa
2022	J	`jnl`	Secure Register Allocation for Trusted Code Generation. IEEE Embed. Syst. Lett. Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, Prabhat Mishra
2021	J	`jnl`	HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Embed. Comput. Syst. Debabrata Senapati, Arnab Sarkar, Chandan Karfa
2021	A	`conf`	HOST: HLS Obfuscations against SMT ATtack. DATE Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri
2021	—	`conf`	Reverse Engineering Register to Variable Mapping in High-level Synthesis. ISVLSI Mohammed Abderehman, Rupak Gupta, Chandan Karfa
2021	J	`jnl`	VP_TT: A value propagation based equivalence checker for testability transformations. IET Softw. Ramanuj Chouksey, Sachin Kumar Maddheshiya, Chandan Karfa
2020	—	`conf`	Automatic Inverse Operation Detection and its Impact in High-level Synthesis. VDAT Pankaj Kumar Kalita, Ramanuj Chouksey, Chandan Karfa
2020	J	`jnl`	Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020	J	`jnl`	Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. IEEE Trans. Very Large Scale Integr. Syst. Surajit Das, Chandan Karfa, Santosh Biswas
2020	A	`conf`	Is Register Transfer Level Locking Secure? DATE Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri
2020	—	`conf`	SAT Based Partial Attack on Compound Logic Locking. AsianHOST Melbin John, Aadil Hoda, Ramanuj Chouksey, Chandan Karfa
2020	J	`jnl`	Verification of Scheduling of Conditional Behaviors in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Ramanuj Chouksey, Chandan Karfa
2019	J	`jnl`	A Quick Introduction to Functional Verification of Array-Intensive Programs. CoRR Kunal Banerjee, Chandan Karfa
2019	J	`jnl`	Counter-example generation procedure for path-based equivalence checkers. IET Softw. Ramanuj Chouksey, Chandan Karfa, Kunal Banerjee, Pankaj Kumar Kalita, Purandar Bhaduri
2019	—	`conf`	Formal Verification of Optimizing Transformations during High-level Synthesis. ISEC Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
2019	Misc	`conf`	Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. VLSID Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
2019	J	`jnl`	Translation Validation of Code Motion Transformations Involving Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
2019	—	`conf`	User Guided Register Manipulation in Digital Circuits. VDAT Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa
2019	J	`jnl`	Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
2018	—	`conf`	Automatic detection of inverse operations while avoiding loop unrolling. ICSE (Companion Volume) Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa, Pankaj Kumar Kalita
2018	—	`conf`	Compiler-agnostic Translation Validation. ISEC Kunal Banerjee, Chandan Karfa
2017	—	`conf`	Translation Validation of Loop Invariant Code Optimizations Involving False Computations. VDAT Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
2017	—	`conf`	xMAS Based Accurate Modeling and Progress Verification of NoCs. VDAT Surajit Das, Chandan Karfa, Santosh Biswas
2014	J	`jnl`	Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013	Misc	`conf`	Verification of KPN Level Transformations. VLSI Design Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013	J	`jnl`	Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2012	—	`conf`	A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
2012	J	`jnl`	Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
2011	—	`conf`	Equivalence Checking of Array-Intensive Programs. ISVLSI Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal
2011	—	`conf`	Verification of Register Transfer Level Low Power Transformations. ISVLSI Chandan Karfa, Chitta Mandal, Dipankar Sarkar
2010	—	`conf`	Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2010	J	`jnl`	Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Dipankar Sarkar, Chitta Mandal
2008	J	`jnl`	An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar
2007	—	`conf`	Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
2007	—	`conf`	Register Sharing Verification During Data-Path Synthesis. ICCTA Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
2006	—	`conf`	A Formal Verification Method of Scheduling in High-level Synthesis. ISQED Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
2006	C	`conf`	Fairness of transitions in diagnosability analysis of hybrid systems. ACC Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
2006	—	`conf`	Verification of Scheduling in High-level Synthesis. ISVLSI Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade