Chan-Hsiang Weng

12 papers Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2019 — conf
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS.
VLSI Circuits
Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang
2019 — conf
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.
ISSCC
Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu
2017 J jnl
A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chan-Hsiang Weng, Yung-Yu Lin, Tsung-Hsien Lin
2016 J jnl
A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer.
IEEE J. Solid State Circuits
Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Tsung-Hsien Lin
2015 — conf
A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer.
VLSI-DAT
Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin
2015 — conf
A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS.
A-SSCC
Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin
2015 J jnl
A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C
IEEE J. Solid State Circuits
Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
2014 — conf
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C.
A-SSCC
Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
2014 J jnl
A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs
Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin
2014 — conf
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS.
VLSIC
Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin
2013 — conf
A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer.
VLSI-DAT
Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin
2011 J jnl
A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin