Chak-Wa Pui - RankMe

17 papers A* 2A 5Journal 4Unranked 6

Year	Rank	Type	Title / Venue / Authors
2023	A	`conf`	TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. DATE Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao
2022	A	`conf`	Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. ICCAD Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng
2021	—	`conf`	Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young
2020	A*	`conf`	CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young
2020	J	`jnl`	Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young
2020	J	`jnl`	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. Chak-Wa Pui, Evangeline F. Y. Young
2020	J	`jnl`	Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
2019	—	`conf`	An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young
2019	—	`conf`	Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young
2019	—	`conf`	Device Layer-Aware Analytical Placement for Analog Circuits. ISPD Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019	A	`conf`	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD Chak-Wa Pui, Evangeline F. Y. Young
2018	—	`conf`	A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young
2018	J	`jnl`	RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu
2018	—	`conf`	Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
2017	A	`conf`	Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu
2016	A*	`conf`	Legalization algorithm for multiple-row height standard cell design. DAC Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young
2016	A	`conf`	RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu