Cenlin Duan - RankMe

18 papers A* 2Journal 15Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2026	J	`jnl`	CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures. IEEE Trans. Computers Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2026	J	`jnl`	Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2026	—	`conf`	MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator. ASP-DAC Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao May, Jianlei Yang
2025	J	`jnl`	ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments. CoRR Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2025	A*	`conf`	CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. DAC Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025	J	`jnl`	CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. CoRR Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025	J	`jnl`	CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures. CoRR Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2025	J	`jnl`	Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity. CoRR Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025	J	`jnl`	HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference. CoRR Cenlin Duan, Jianlei Yang, Rubing Yang, Yikun Wang, Yiou Wang, Lingkun Long, Yingjie Qi, Xiaolin He, Ao Zhou, Xueyan Wang, Weisheng Zhao
2025	J	`jnl`	MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator. CoRR Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao Ma, Jianlei Yang
2024	J	`jnl`	DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024	J	`jnl`	HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. CoRR Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024	J	`jnl`	HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. IEEE Trans. Computers Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024	A*	`conf`	Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. DAC Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024	J	`jnl`	Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. CoRR Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2023	J	`jnl`	DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2022	J	`jnl`	Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang