Cecilia Metra - RankMe

169 papers A 23B 3C 21Misc 4Journal 68Unranked 50

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability. DSD Giovanni Agosta, Enrico Bini, Davide Baroffio, Carlo Brandolese, Michele Castrovilli, Daniele Cattaneo, Daniele Cesarini, William Fornaciari, Andrea Galimberti, Alberto Garfagnini, Arsenii Gavrikov, Francesco Iannone, Marco Lapegna, Tomas Antonio Lopez, Gabriele Magnani, Gabriele Mencagli, Cecilia Metra, Martin Eugenio Omana, Filippo Palombi, Federico Reghenzani, Josie E. Rodriguez Condia, A. Serafini, Matteo Sonza Reorda, Davide Zoni, Giuseppe Zummo
2025	J	`jnl`	Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays. IEEE Access Marco Grossi, Martin Omaña, Cecilia Metra, Andrea Acquaviva
2025	C	`conf`	On-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems. IOLTS Martin Omaña, A. Menghi, A. Stefani, E. Vicini, Cecilia Metra, G. Froio, S. Petrucci
2025	J	`jnl`	Risks of Silent Data Corruption Due to the Combined Effects of Latent Faults and Aging Phenomena Affecting FinFET-Based ICs. IEEE Access Martin Omaña, Yashwanthi Venigalla, Matteo Naldi, Cecilia Metra
2025	J	`jnl`	The Emerging Metaverse: IEEE ISEMV 2024 Retrospective and Future Directions. Computer Louis Nisiotis, Cecilia Metra, Jyotika Athavale, Dejan S. Milojicic, Stephen Dukes, Jeewika Ranaweera, Sin-Kuen Hawkins
2024	—	`conf`	A PCI Express Based Data Acquisition System for the Monitoring of Code Traces of RISC-V Microprocessors. ICSRS Marco Grossi, Simone Manoni, Emanuele Parisi, Martin Omaña, Cecilia Metra, Fabrizio Alfonsi, Alessandro Gabrielli, Andrea Acquaviva
2024	C	`conf`	On the Reliability of Clock Monitoring Units for Safety Critical Applications' Microcontrollers. IOLTS M. Zhupa, M. Naldi, Maira Omaña, Cecilia Metra
2024	C	`conf`	Reliability of AI in Predicting the State of Health of Li-Ion Batteries IOLTS Sara Cretí, Martin Omaña, Cecilia Metra, Gianni Borelli
2024	C	`conf`	Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches. IOLTS Martin Omaña, A. Manfredi, Cecilia Metra, R. Locatelli, M. Chiavacci, S. Petrucci
2023	—	`conf`	RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. SAMOS William Fornaciari, Federico Reghenzani, Federico Terraneo, Davide Baroffio, Cecilia Metra, Martin Omaña, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Robert Birke, Iacopo Colonnelli, Gianluca Mittone, Marco Aldinucci, Gabriele Mencagli, Francesco Iannone, Filippo Palombi, Giuseppe Zummo, Daniele Cesarini, Federico Tesser
2022	—	`conf`	Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection. LATS Fabrizio Finelli, Martin Omaña, Cecilia Metra
2022	C	`conf`	Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. IOLTS Marco Grossi, Martin Omaña, Daniele Rossi, Biagio Marzulli, Cecilia Metra
2022	J	`jnl`	Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions. IEEE Trans. Emerg. Top. Comput. Martin Omaña, Sejuti Bardhan, Cecilia Metra
2020	J	`jnl`	Guest Editor's Introduction: Special Section on High Dependability Systems. IEEE Trans. Emerg. Top. Comput. Cecilia Metra, Matteo Sonza Reorda
2020	J	`jnl`	Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. Cecilia Metra
2019	J	`jnl`	Fault-Tolerant Inverters for Reliable Photovoltaic Systems. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra
2019	J	`jnl`	Low-Cost Strategy for Bus Propagation Delay Reduction. J. Electron. Test. Martin Omaña, S. Govindaraj, Cecilia Metra
2019	J	`jnl`	Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. Cecilia Metra
2019	J	`jnl`	Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage. IEEE Trans. Emerg. Top. Comput. Rob Aitken, Cecilia Metra
2019	J	`jnl`	The 2019 IEEE Computer Society: Hit Target on Member Satisfaction and Technical Excellence. Computer Cecilia Metra
2019	J	`jnl`	The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence. Computer Cecilia Metra
2018	J	`jnl`	Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness. IEEE Trans. Emerg. Top. Comput. Martin Omaña, TusharaSandeep Edara, Cecilia Metra
2018	J	`jnl`	Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. Cecilia Metra
2017	J	`jnl`	New Approaches for Power Binning of High Performance Microprocessors. IEEE Trans. Computers Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche
2017	J	`jnl`	Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
2016	A	`conf`	Inverters' self-checking monitors for reliable photovoltaic systems. DATE Martin Omaña, A. Fiore, Cecilia Metra
2016	J	`jnl`	Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche
2015	J	`jnl`	Impact of Bias Temperature Instability on Soft Error Susceptibility. IEEE Trans. Very Large Scale Integr. Syst. Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella
2015	—	`conf`	Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. ATS Michael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña, Cecilia Metra, Hans-Joachim Wunderlich
2015	J	`jnl`	Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam
2015	J	`jnl`	Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. IEEE Trans. Very Large Scale Integr. Syst. Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra
2014	J	`jnl`	Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
2014	—	`conf`	Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
2013	J	`jnl`	Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Daniele Rossi, Daniele Giaffreda, Roberto Specchia, Cecilia Metra, Marcin Marzencki, Bozena Kaminska
2013	J	`jnl`	Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
2013	J	`jnl`	Low Cost NBTI Degradation Detection and Masking Approaches. IEEE Trans. Computers Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra
2013	B	`conf`	Novel approach to reduce power droop during scan-based logic BIST. ETS Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache
2012	—	`conf`	Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. DFT Martin Omaña, Daniele Rossi, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi
2012	—	`conf`	High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella
2012	J	`jnl`	New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2011	A	`conf`	Error correcting code analysis for cache memory high reliability and performance. DATE Daniele Rossi, N. Timoncini, M. Spica, Cecilia Metra
2011	J	`jnl`	Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. IEEE Trans. Computers Cecilia Metra, Rajesh Galivanche
2011	—	`conf`	Impact of Aging Phenomena on Soft Error Susceptibility. DFT Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella
2011	J	`jnl`	Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam
2011	—	`conf`	Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. DFT Daniele Giaffreda, Martin Omaña, Daniele Rossi, Cecilia Metra
2010	J	`jnl`	High-Performance Robust Latches. IEEE Trans. Computers Martin Omaña, Daniele Rossi, Cecilia Metra
2010	—	`conf`	Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
2010	—	`conf`	Novel low-cost aging sensor. Conf. Computing Frontiers Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra
2010	—	`conf`	On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman
2010	—	`conf`	Secure communication protocol for wireless sensor networks. EWDTS Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra
2010	—	`conf`	Transient Fault and Soft Error On-die Monitoring Scheme. DFT Daniele Rossi, Martin Omaña, Cecilia Metra
2009	J	`jnl`	Accurate Linear Model for SET Critical Charge Estimation. IEEE Trans. Very Large Scale Integr. Syst. Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
2009	—	`conf`	Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. DFT Martin Omaña, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska
2009	J	`jnl`	Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates. J. Electron. Test. Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi
2009	—	`conf`	Novel High Speed Robust Latch. DFT Martin Omaña, Daniele Rossi, Cecilia Metra
2009	J	`jnl`	Testing Resistive Opens and Bridging Faults Through Pulse Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michele Favalli, Cecilia Metra
2008	J	`jnl`	Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. J. Electron. Test. Daniele Rossi, Martin Omaña, Cecilia Metra
2008	B	`conf`	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
2008	—	`conf`	Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam
2008	J	`jnl`	Power Consumption of Fault Tolerant Busses. IEEE Trans. Very Large Scale Integr. Syst. Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra
2008	J	`jnl`	Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. J. Electron. Test. Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi
2008	B	`conf`	Risks for Signal Integrity in System in Package and Possible Remedies. ETS Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli
2008	J	`jnl`	Simultaneous Switching Noise: The Relation between Bus Layout and Coding. IEEE Des. Test Comput. Daniele Rossi, André K. Nieuwland, Cecilia Metra
2007	C	`conf`	Configurable Error Control Scheme for NoC Signal Integrity. IOLTS Daniele Rossi, Paolo Angelini, Cecilia Metra
2007	J	`jnl`	Guest Editors' Introduction: The State of the Art in Nanoscale CAD. IEEE Des. Test Comput. Fabrizio Lombardi, Cecilia Metra
2007	A	`conf`	Interactive presentation: Pulse propagation for the detection of small delay defects. DATE Michele Favalli, Cecilia Metra
2007	J	`jnl`	Latch Susceptibility to Transient Faults and New Hardening Approach. IEEE Trans. Computers Martin Omaña, Daniele Rossi, Cecilia Metra
2007	Misc	`conf`	Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2007	A	`conf`	Novel compensation scheme for local clocks of high performance microprocessors. ITC Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2007	—	`conf`	Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. DFT Jing Huang, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi
2007	J	`jnl`	Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers Cecilia Metra, Daniele Rossi, T. M. Mak
2006	A	`conf`	Analysis of the impact of bus implemented EDCs on on-chip SSN. DATE Daniele Rossi, Carlo Steiner, Cecilia Metra
2006	C	`conf`	Can Clock Faults be Detected Through Functional Test? DDECS Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
2006	C	`conf`	Checker No-Harm Alarm Robustness. IOLTS Daniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni
2006	J	`jnl`	Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). IEEE Trans. Computers Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi
2006	A	`conf`	Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. DATE Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2006	C	`conf`	Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2006	—	`conf`	Testing Reversible 1D Arrays for Molecular QCA. DFT Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi
2005	C	`conf`	Coding Techniques for Low Switching Noise in Fault Tolerant Busses. IOLTS André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra
2005	J	`jnl`	Exploiting ECC Redundancy to Minimize Crosstalk Impact. IEEE Des. Test Comput. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
2005	C	`conf`	Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. IOLTS Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
2005	Misc	`conf`	Low Cost Scheme for On-Line Clock Skew Compensation. VTS Martin Omaña, Daniele Rossi, Cecilia Metra
2005	J	`jnl`	Low Cost and High Speed Embedded Two-Rail Code Checker. IEEE Trans. Computers Martin Omaña, Daniele Rossi, Cecilia Metra
2005	—	`conf`	Multiple Transient Faults in Logic: An Issue for Next Generation ICs. DFT Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra
2005	J	`jnl`	New ECC for Crosstalk Impact Minimization. IEEE Des. Test Comput. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
2005	J	`jnl`	Novel on-chip circuit for jitter testing in high-speed PLLs. IEEE Trans. Instrum. Meas. José Manuel Cazeaux, Martin Omaña, Cecilia Metra
2005	C	`conf`	On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. IOLTS José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
2005	C	`conf`	On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. IOLTS Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni
2005	J	`jnl`	Self-Checking Voter for High Speed TMR Systems. J. Electron. Test. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2005	—	`conf`	The Other Side of the Timing Equation: a Result of Clock Faults. DFT Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2004	A	`conf`	Are Our Design for Testability Features Fault Secure? DATE Cecilia Metra, T. M. Mak, Martin Omaña
2004	—	`conf`	Fast and Low-Cost Clock Deskew Buffer. DFT Martin Omaña, Daniele Rossi, Cecilia Metra
2004	—	`conf`	Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers Cecilia Metra, T. M. Mak, Martin Omaña
2004	J	`jnl`	Guest Editorial. J. Electron. Test. Cecilia Metra, Matteo Sonza Reorda
2004	J	`jnl`	Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. IEEE Des. Test Comput. André Ivanov, Fabrizio Lombardi, Cecilia Metra
2004	C	`conf`	Hardware Reconfiguration Scheme for High Availability Systems. IOLTS Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni
2004	C	`conf`	Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. IOLTS Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
2004	J	`jnl`	Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
2004	C	`conf`	Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. IOLTS José Manuel Cazeaux, Martin Omaña, Cecilia Metra
2004	J	`jnl`	Model for Transient Fault Susceptibility of Combinational Circuits. J. Electron. Test. Martin Omaña, Daniele Rossi, Cecilia Metra
2004	C	`conf`	New High Speed CMOS Self-Checking Voter. IOLTS José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2004	A	`conf`	Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC Cecilia Metra, T. M. Mak, Martin Omaña
2004	J	`jnl`	TMR voting in the presence of crosstalk faults at the voter inputs. IEEE Trans. Reliab. Michele Favalli, Cecilia Metra
2003	C	`conf`	A Model for Transient Fault Propagation in Combinatorial Logic. IOLTS Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra
2003	—	`conf`	Automatic Modification of Sequential Circuits for Self-Checking Implementation. DFT Cecilia Metra, Stefano Di Francescantonio, Martin Omaña
2003	—	`conf`	Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT Cecilia Metra, T. M. Mak, Daniele Rossi
2003	J	`jnl`	Concurrent detection of power supply noise. IEEE Trans. Reliab. Cecilia Metra, Luca Schiano, Michele Favalli
2003	C	`conf`	Crosstalk Effect Minimization for Encoded Busses. IOLTS L. Di Silvio, Daniele Rossi, Cecilia Metra
2003	—	`conf`	Error Correcting Codes for Crosstalk Effect Minimization. DFT Daniele Rossi, S. Cavallotti, Cecilia Metra
2003	J	`jnl`	Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. J. Electron. Test. Daniele Rossi, Cecilia Metra
2003	J	`jnl`	Guest Editorial. J. Electron. Test. Cecilia Metra, Matteo Sonza Reorda
2003	A	`conf`	High Speed and Highly Testable Parallel Two-Rail Code Checker. DATE Martin Omaña, Daniele Rossi, Cecilia Metra
2003	A	`conf`	Novel Transient Fault Hardened Static Latch. ITC Martin Omaña, Daniele Rossi, Cecilia Metra
2003	C	`conf`	Power Consumption of Fault Tolerant Codes: the Active Elements. IOLTS Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra
2003	J	`jnl`	Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. Microelectron. J. Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò
2003	J	`jnl`	Self-checking design, implementation, and measurement of a controller for track-side railway systems. IEEE Trans. Instrum. Meas. Luca Schiano, Cecilia Metra, Diego Marino
2002	A	`conf`	Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
2002	—	`conf`	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. IOLTW Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra
2002	—	`conf`	Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. IOLTW Luca Schiano, Cecilia Metra, Diego Marino
2002	—	`conf`	Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. MTDT Luca Schiano, Cecilia Metra, Diego Marino
2002	—	`conf`	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. IOLTW Daniele Rossi, Cecilia Metra, Bruno Riccò
2002	—	`conf`	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. MTDT Daniele Rossi, Cecilia Metra, Bruno Riccò
2002	J	`jnl`	Guest Editorial. J. Electron. Test. Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra
2002	J	`jnl`	On-Chip Clock Faults' Detector. J. Electron. Test. Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò
2002	—	`conf`	On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. DFT Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale
2002	J	`jnl`	Online Testing Approach for Very Deep-Submicron ICs. IEEE Des. Test Comput. Michele Favalli, Cecilia Metra
2002	A	`conf`	Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. DATE Michele Favalli, Cecilia Metra
2002	A	`conf`	Self-Checking Scheme for the On-Line Testing of Power Supply Noise. DATE Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli
2002	J	`jnl`	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. J. Electron. Test. Michele Favalli, Cecilia Metra
2001	—	`conf`	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
2001	J	`jnl`	Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems. IEEE Des. Test Comput. Fabrizio Lombardi, Cecilia Metra
2001	—	`conf`	Novel Fault-Tolerant Adder Design for FPGA-Based Systems. IOLTW Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
2001	A	`conf`	On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. ITC Cecilia Metra, Andrea Pagano, Bruno Riccò
2001	A	`conf`	Optimization of error detecting codes for the detection of crosstalk originated errors. DATE Michele Favalli, Cecilia Metra
2001	—	`conf`	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. IOLTW Michele Favalli, Cecilia Metra
2000	—	`conf`	Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. DFT Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
2000	J	`jnl`	Bridging Faults in Pipelined Circuits. J. Electron. Test. Michele Favalli, Cecilia Metra
2000	J	`jnl`	Intermediacy Prediction for High Speed Berger Code Checkers. J. Electron. Test. Cecilia Metra, Jien-Chung Lo
2000	A	`conf`	On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. DATE Cecilia Metra, Michele Favalli, Bruno Riccò
2000	J	`jnl`	Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. IEEE Trans. Computers Cecilia Metra, Michele Favalli, Bruno Riccò
2000	J	`jnl`	Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. VLSI Design Cecilia Metra, Michele Favalli, Bruno Riccò
1999	J	`jnl`	Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. IEEE Trans. Very Large Scale Integr. Syst. Michele Favalli, Cecilia Metra
1999	A	`conf`	On the Design of Self-Checking Functional Units Based on Shannon Circuits. DATE Michele Favalli, Cecilia Metra
1999	A	`conf`	Self-checking scheme for very fast clocks' skew correction. ITC Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò
1999	—	`conf`	Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. DFT Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
1998	J	`jnl`	Concurrent Checking of Clock Signal Correctness. IEEE Des. Test Comput. Cecilia Metra, Michele Favalli, Bruno Riccò
1998	—	`conf`	Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. DFT Sergio D'Angelo, Cecilia Metra, Sandro Pastore, A. Pogutz, Giacomo R. Sechi
1998	A	`conf`	Highly Testable and Compact 1-out-of-n Code Checker with Single Output. DATE Cecilia Metra, Michele Favalli, Bruno Riccò
1998	A	`conf`	Novel Technique for Testing FPGAs. DATE Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
1998	A	`conf`	On-line detection of logic errors due to crosstalk, delay, and transient faults. ITC Cecilia Metra, Michele Favalli, Bruno Riccò
1998	—	`conf`	Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1997	—	`conf`	Compact and low power on-line self-testing voting scheme. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1997	—	`conf`	Fast and area-time efficient Berger code checkers. DFT Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra
1997	Misc	`conf`	Highly testable and compact single output comparator. VTS Cecilia Metra, Michele Favalli, Bruno Riccò
1997	—	`conf`	Low-level error recovery mechanism for self-checking sequential circuits. DFT Michele Favalli, Cecilia Metra
1997	A	`conf`	On-Line Testing Scheme for Clock's Faults. ITC Cecilia Metra, Michele Favalli, Bruno Riccò
1997	J	`jnl`	On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
1997	—	`conf`	Testing scheme for IC's clocks. ED&TC Michele Favalli, Cecilia Metra
1996	—	`conf`	Compact and Highly Testable Error Indicator for Self-Checking Circuits. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1996	Misc	`conf`	Embedded two-rail checkers with on-line testing ability. VTS Cecilia Metra, Michele Favalli, Bruno Riccò
1996	J	`jnl`	Sensing circuit for on-line detection of delay faults. IEEE Trans. Very Large Scale Integr. Syst. Michele Favalli, Cecilia Metra
1996	—	`conf`	Tree Checkers for Applications with Low Power-Delay Requirements. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1995	J	`jnl`	Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J. Electron. Test. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
1995	—	`conf`	Novel Berger code checker. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1994	—	`conf`	CMOS Self Checking Circuits with Faulty Sequential Functional Block. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1994	—	`conf`	Highly Testable and Compact 1-out-of-n CMOS Checkers. DFT Cecilia Metra, Michele Favalli, Bruno Riccò
1993	—	`conf`	A Highly Testable 1-out-of-3 CMOS Checker. DFT Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
1993	—	`conf`	Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. DFT Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
1992	A	`conf`	CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. ITC Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò