Carlos Tokunaga

48 papers A* 1A 3C 1Journal 17Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	10.6 A Hybrid-Bonded 12.1Tops/mm ISSCC Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz
2026	J	`jnl`	A Compact, Highly-Digital Sensor-Fusion-Based Joint V IEEE J. Solid State Circuits Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser A. Kurd, Visvesh S. Sathe
2025	—	`conf`	8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS. ISSCC Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser A. Kurd, Visvesh Sathe
2025	—	`conf`	A Comparative Analysis of Aging Effects on Computing-in-Memory Systems in 28nm CMOS. IRPS Shida Zhang, Wei-Chun Wang, Carlos Tokunaga, Saibal Mukhopadhyay
2024	J	`jnl`	A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew
2024	—	`conf`	Measurement of Aging Effect in a Digitally Controlled Inductive Voltage Regulator in 65nm. IRPS Shida Zhang, Nael Mizanur Rahman, Wei Chun Wang, Narasimha Vasishta Kidambi, Carlos Tokunaga, Saibal Mukhopadhyay
2023	—	`conf`	A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew
2023	J	`jnl`	An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. IEEE J. Solid State Circuits Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy
2022	—	`conf`	An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. VLSI Technology and Circuits Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy
2022	A	`conf`	Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator. ISLPED Shida Zhang, Nael Mizanur Rahman, Venkata Chaitanya Krishna Chekuri, Carlos Tokunaga, Saibal Mukhopadhyay
2022	A*	`conf`	Improving compute in-memory ECC reliability with successive correction. DAC Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2021	J	`jnl`	A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim
2021	—	`conf`	CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2020	—	`conf`	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
2019	J	`jnl`	An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	—	`conf`	An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2017	J	`jnl`	Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	—	`conf`	8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2016	—	`conf`	Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016	J	`jnl`	Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015	—	`conf`	4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2015	—	`conf`	8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015	—	`conf`	A fully integrated charge sharing active decap scheme for power supply noise suppression. SoCC Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah
2015	—	`conf`	Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. CICC Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014	—	`conf`	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2013	J	`jnl`	A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. IEEE J. Solid State Circuits Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De
2013	J	`jnl`	A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz
2013	J	`jnl`	Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De
2012	—	`conf`	A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. CICC Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De
2012	—	`conf`	A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	J	`jnl`	Securing Encryption Systems With a Switched Capacitor Current Equalizer. IEEE J. Solid State Circuits Carlos Tokunaga, David T. Blaauw
2009	J	`jnl`	RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. Solid State Circuits Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw
2009	—	`conf`	Secure AES engine with a local switched-capacitor current equalizer. ISSCC Carlos Tokunaga, David T. Blaauw
2008	C	`conf`	Low-voltage circuit design for widespread sensing applications. ISCAS Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall D. Wise, Ann Marie Sastry, David T. Blaauw, Dennis Sylvester
2008	—	`conf`	Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. ISSCC David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull
2008	—	`conf`	Timing yield enhancement through soft edge flip-flop based design. CICC Michael Wieckowski, Young Min Park, Carlos Tokunaga, Dong Woon Kim, Zhiyoong Foo, Dennis Sylvester, David T. Blaauw
2008	J	`jnl`	True Random Number Generator With a Metastability-Based Quality Control. IEEE J. Solid State Circuits Carlos Tokunaga, David T. Blaauw, Trevor N. Mudge
2007	—	`conf`	Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
2007	—	`conf`	True Random Number Generator with a Metastability-Based Quality Control. ISSCC Carlos Tokunaga, David T. Blaauw, Trevor N. Mudge