Carlos Carreras

51 papers B 2C 4Misc 2Journal 21Unranked 22

Year	Rank	Type	Title / Venue / Authors
2019	B	`conf`	High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. FPL Roberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena
2019	J	`jnl`	Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. Roberto Sierra, Carlos Carreras, Gabriel Caffarena
2018	—	`conf`	Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. PATMOS Roberto Sierra, Carlos Carreras, Gabriel Caffarena
2015	J	`jnl`	A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario
2014	J	`jnl`	Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. IEEE Trans. Ind. Informatics Bojan Jovanovic, Ruzica Jevtic, Carlos Carreras
2014	J	`jnl`	Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. J. Syst. Archit. Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra
2012	J	`jnl`	A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integr. Ruzica Jevtic, Carlos Carreras
2012	J	`jnl`	A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Signal Process. Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
2012	J	`jnl`	Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. J. Circuits Syst. Comput. Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
2012	—	`conf`	Turning control flow graphs into function calls: Code generation for heterogeneous architectures. HPCS Pablo Barrio, Carlos Carreras, Roberto Sierra, Tobias Kenter, Christian Plessl
2011	C	`conf`	Mesh traversal and sorting for efficient memory usage in scientific codes. IPCCC Pablo Barrio, Carlos Carreras
2011	J	`jnl`	Power Measurement Methodology for FPGA Devices. IEEE Trans. Instrum. Meas. Ruzica Jevtic, Carlos Carreras
2011	—	`conf`	Power estimation of dividers implemented in FPGAs. ACM Great Lakes Symposium on VLSI Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras
2010	J	`jnl`	A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems. J. Comput. Networks Commun. Javier Gonzalez Bayon, Carlos Carreras, Ove Edfors
2010	C	`conf`	Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC Gabriel Caffarena, Carlos Carreras
2010	—	`conf`	Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras
2010	C	`conf`	Fast fixed-point optimization of DSP algorithms. VLSI-SoC Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
2010	J	`jnl`	Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electron. Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
2010	J	`jnl`	Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Ruzica Jevtic, Carlos Carreras
2010	—	`conf`	Precision-wise architectural synthesis of DSP circuits. EUSIPCO Gabriel Caffarena, Carlos Carreras
2010	J	`jnl`	SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
2010	—	`conf`	SQNR estimation of non-linear fixed-point algorithms. EUSIPCO Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras
2009	—	`conf`	A Practical Method for Testing High-Speed Networking Hardware Architectures. ICNS Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras, Atta Badii
2009	J	`jnl`	Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
2009	Misc	`conf`	Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena, Vladimir M. Milovanovic, Carlos Carreras, Jelena Popovic
2009	—	`conf`	Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
2008	—	`conf`	A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. ReConFig Ruzica Jevtic, Carlos Carreras, Domenik Helms
2008	—	`conf`	Analytical High-Level Power Model for LUT-Based Components. PATMOS Ruzica Jevtic, Carlos Carreras
2008	J	`jnl`	Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
2008	—	`conf`	Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
2007	—	`conf`	A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. ERSA Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
2007	—	`conf`	Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. SECURWARE Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
2007	J	`jnl`	Fpga Acceleration for DNA Sequence Alignment. J. Circuits Syst. Comput. Gabriel Caffarena, Carlos E. Pedreira, Carlos Carreras, Slobodan Bojanic, Octavio Nieto-Taladriz
2007	J	`jnl`	Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2007	—	`conf`	Switching Activity Models for Power Estimation in FPGA Multipliers. ARC Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
2006	B	`conf`	High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2006	J	`jnl`	Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz
2006	—	`conf`	Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2005	C	`conf`	Extension versus bending for continuum robots. ICINCO Robin McDonnell, George Grimes, Ian D. Walker, Carlos Carreras
2004	Misc	`conf`	A Generator of High-Speed Floating-Point Modules. FCCM Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
2004	—	`conf`	Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
2004	—	`conf`	Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. EUSIPCO Gabriel Caffarena, Angel Fernández, Carlos Carreras, Octavio Nieto-Taladriz
2003	J	`jnl`	Diseño y Análisis Comparativo de un Microprocesador RISC Básico y Controladores Periféricos Especiales. Res. Comput. Sci. Carlos Carreras, Gerardo Leyva, I. De la Parra, J. Esparza, R. Jaramillo
2003	—	`conf`	Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz
2003	J	`jnl`	Tarjeta Didáctica para Implementación de Circuitos Digitales en FPGA. Res. Comput. Sci. Carlos Carreras, Gerardo Leyva, Octavio Nieto-Taladriz, R. Jaramillo
2001	J	`jnl`	Interval methods for fault-tree analysis in robotics. IEEE Trans. Reliab. Carlos Carreras, Ian D. Walker
2000	—	`conf`	Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. SARA Carlos Carreras, Manuel V. Hermenegildo
2000	J	`jnl`	On interval methods applied to robot reliability quantification. Reliab. Eng. Syst. Saf. Carlos Carreras, Ian D. Walker
1999	—	`conf`	Bit-Width Selection for Data-Path Implementations. ISSS Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz
1996	—	`conf`	A Co-Design Methodology Based on Formal Specification and High-level Estimation. CODES Carlos Carreras, Juan Carlos López, María Luisa López Vallejo, Luis Sánchez, Carlos Delgado Kloos, Natividad Martínez Madrid
1994	—	`conf`	Analytic Model of a Cache Only Memory Architecture. PARLE Carlos Carreras, Carlos A. López Bario, Manuel V. Hermenegildo