Carles Hernández

104 papers A* 6A 19B 11C 14Misc 3Journal 36Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	HashTAG With CALM: Low-Overhead Hardware Support for Inter-Task Eviction Monitoring. IEEE Trans. Parallel Distributed Syst. Pablo Andreu, Pedro López, Carles Hernández
2026	J	`jnl`	Peformance Isolation for Inference Processes in Edge GPU Systems. CoRR Juan José Martín, José Flich, Carles Hernández
2026	J	`jnl`	TinyATD: Compressing Auxiliary Tag Directories using tag hashing and set-sampling. J. Syst. Archit. Pablo Andreu, Pedro López, Carles Hernández
2025	J	`jnl`	Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs. Future Gener. Comput. Syst. Pablo Andreu, Sergi Alcaide, Pedro López, Jaume Abella, Carles Hernández
2025	J	`jnl`	Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference. J. Supercomput. Izan Catalán, José Flich, Carles Hernández
2025	B	`conf`	Improving Out-of-Distribution Detection via Test-Time Augmentation. SAFECOMP Imanol Allende, Nicholas Mc Guire, Javier del Campo, Carles Hernández
2025	J	`jnl`	Leveraging HLS to Design a Versatile & High-Performance Classic McEliece Accelerator. ACM Trans. Embed. Comput. Syst. Vatistas Kostalabros, Jordi Ribes-González, Xavier Carril, Oriol Farràs, Carles Hernández, Miquel Moretó
2024	—	`conf`	A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. ARC Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández
2024	J	`jnl`	Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium. ACM Trans. Reconfigurable Technol. Syst. Xavier Carril, Charalampos Kardaris, Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó
2024	J	`jnl`	Hashing ATD Tags for Low-Overhead Safe Contention Monitoring. IEEE Comput. Archit. Lett. Pablo Andreu, Pedro López, Carles Hernández
2023	B	`conf`	A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric
2023	J	`jnl`	Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems. ACM Trans. Design Autom. Electr. Syst. Jordi Cardona, Carles Hernández, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla
2023	A	`conf`	BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. DATE Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández
2023	A	`conf`	NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
2022	J	`jnl`	A Security Model for Randomization-based Protected Caches. IACR Cryptol. ePrint Arch. Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó
2022	J	`jnl`	A Security Model for Randomization-based Protected Caches. IACR Trans. Cryptogr. Hardw. Embed. Syst. Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó
2022	J	`jnl`	Achieving Diverse Redundancy for GPU Kernels. IEEE Trans. Emerg. Top. Comput. Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
2022	—	`conf`	DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa
2022	B	`conf`	Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. ICIP José Flich, Laura Medina, Izan Catalán, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau, David Briand
2022	J	`jnl`	End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. CoRR Pablo Andreu, Carles Hernández, Tomás Picornell, Pedro López, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella
2022	A	`conf`	SafeSU-2: a Safe Statistics Unit for Space MPSoCs. DATE Guillem Cabo, Sergi Alcaide, Carles Hernández, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella
2022	A	`conf`	The SELENE Deep Learning Acceleration Framework for Safety-related Applications. DATE Laura Medina, Salva Carrion, Pablo Andreu, Tomás Picornell, José Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess, Herbert Taucher
2021	J	`jnl`	Enforcing Predictability of Many-Cores With DCFNoC. IEEE Trans. Computers Tomás Picornell, José Flich, Carles Hernández, José Duato
2021	A	`conf`	From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. DATE José Flich, Rafael Tornero, David Rodriguez, Davide Russo, José Maria Martínez, Carles Hernández
2021	B	`conf`	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. FPL Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández
2021	A	`conf`	Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández
2021	J	`jnl`	Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives. ACM Comput. Surv. Ramon Canal, Carles Hernández, Rafael Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech Piatek, Jaume Abella
2021	B	`conf`	SafeSU: an Extended Statistics Unit for Multicore Timing Interference. ETS Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moretó, Carles Hernández, Jaume Abella
2021	B	`conf`	Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
2021	J	`jnl`	Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. IEEE Trans. Sustain. Comput. David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2020	—	`conf`	An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa
2020	—	`conf`	Distributed Training on a Highly Heterogeneous HPC System. SAMOS José Flich, Carles Hernández, Eduardo Quiñones, Roberto Paredes
2020	J	`jnl`	HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory. IEEE Access Tomás Picornell, José Flich, José Duato, Carles Hernández
2020	C	`conf`	SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. DSD Carles Hernández, José Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Lüdemann, Mikel Labayen
2020	—	`conf`	Software-Only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms. DSN (Supplements) Sergi Alcaide Portet, Leonidas Kosmidis, Carles Hernández, Jaume Abella
2020	—	`conf`	Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms. DFT Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
2020	J	`jnl`	The RECIPE approach to challenges in deeply heterogeneous high performance systems. Microprocess. Microsystems Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2020	—	`conf`	Workshop on High-performance Computing Platforms for Dependable Autonomous Systems. DSN Workshops Carles Hernández, Jaume Abella, Mikel Azkarate-askasua, Roman Obermaisser
2019	C	`conf`	An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. DSD David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	C	`conf`	Challenges in Deeply Heterogeneous High Performance Systems. DSD Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2019	A*	`conf`	DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. DAC Tomás Picornell, José Flich, Carles Hernández, José Duato
2019	A	`conf`	High-Integrity GPU Designs for Critical Real-Time Automotive Systems. DATE Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
2019	A	`conf`	LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. DATE Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	J	`jnl`	Locality-aware cache random replacement policies. J. Syst. Archit. Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	A	`conf`	Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement. DATE Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	C	`conf`	Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. DSD David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	J	`jnl`	Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Comput. Surv. Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Tullio Vardanega
2019	J	`jnl`	Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors. IEEE Des. Test David Trilla, Francisco J. Cazorla, Carles Hernández, Jaume Abella
2019	C	`conf`	Software-only Diverse Redundancy on GPUs for Autonomous Driving Platforms. IOLTS Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
2019	J	`jnl`	Time-Randomized Wormhole NoCs for Critical Applications. ACM J. Emerg. Technol. Comput. Syst. Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2019	—	`conf`	Towards limiting the impact of timing anomalies in complex real-time processors. ASP-DAC Pedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla
2018	A*	`conf`	Cache side-channel attacks and time-predictability in high-performance critical real-time systems. DAC David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2018	A	`conf`	Design and integration of hierarchical-placement multi-level caches for real-time systems. DATE Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2018	J	`jnl`	EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jordi Cardona, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2018	J	`jnl`	Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernández, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega
2018	B	`conf`	HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. ECRTS Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2018	A	`conf`	NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores. RTSS Jordi Cardona, Carles Hernández, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
2018	Misc	`conf`	RPR: a random replacement policy with limited pathological replacements. SAC Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2018	J	`jnl`	Reconciling Time Predictability and Performance in Future Computing Systems. IEEE Des. Test Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernández, Tullio Vardanega, Guillem Bernat
2018	—	`conf`	Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
2018	J	`jnl`	Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain. IEEE Micro Sergi Alcaide, Leonidas Kosmidis, Hamid Tabani, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2017	J	`jnl`	Adapting TDMA arbitration for measurement-based probabilistic timing analysis. Microprocess. Microsystems Milos Panic, Jaume Abella, Eduardo Quiñones, Carles Hernández, Theo Ungerer, Francisco J. Cazorla
2017	C	`conf`	Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. DSD Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2017	A*	`conf`	DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. DAC Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella
2017	B	`conf`	Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. ECRTS Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, Franck Wartel
2017	A	`conf`	Design and implementation of a fair credit-based bandwidth sharing scheme for buses. DATE Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2017	Misc	`conf`	MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding. Ada-Europe Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2017	—	`conf`	Modelling bus contention during system early design stages. SIES David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2017	A	`conf`	Probabilistic timing analysis on time-randomized platforms for the space domain. DATE Mikel Fernández, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati
2017	A	`conf`	Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling. RTSS Enrico Mezzetti, Jaume Abella, Carles Hernández, Francisco J. Cazorla
2016	J	`jnl`	Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernández, Andrea Gianarro, Ian Broster, Francisco J. Cazorla
2016	A	`conf`	Improving performance guarantees in wormhole mesh NoC designs. DATE Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla
2016	A	`conf`	Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. RTAS Milos Panic, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla
2016	C	`conf`	Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection. IOLTS Jaime Espinosa, Carles Hernández, Jaume Abella
2016	C	`conf`	PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma
2016	J	`jnl`	Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
2016	A*	`conf`	Random modulo: a new processor cache design for real-time critical systems. DAC Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla
2016	C	`conf`	Resilient random modulo cache memories for probabilistically-analyzable real-time systems. IOLTS David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2016	C	`conf`	pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems. DSD Mladen Slijepcevic, Mikel Fernández, Carles Hernández, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
2015	A*	`conf`	Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. DAC Jaime Espinosa, Carles Hernández, Jaume Abella, David de Andrés, Juan-Carlos Ruiz-Garcia
2015	J	`jnl`	Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. Antoni Roca, Carles Hernández, Mario Lodde, José Flich
2015	C	`conf`	CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. DSD Milos Panic, Eduardo Quiñones, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2015	C	`conf`	Characterizing fault propagation in safety-critical processor designs. IOLTS Jaime Espinosa, Carles Hernández, Jaume Abella
2015	C	`conf`	Enabling TDMA Arbitration in the Context of MBPTA. DSD Milos Panic, Jaume Abella, Carles Hernández, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla
2015	C	`conf`	IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD Irune Agirre, Mikel Azkarate-askasua, Carles Hernández, Jaume Abella, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla
2015	A	`conf`	Low-cost checkpointing in automotive safety-relevant systems. DATE Carles Hernández, Jaume Abella
2015	J	`jnl`	Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carles Hernández, Jaume Abella
2015	—	`conf`	WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, Tullio Vardanega
2014	A*	`conf`	LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems. DAC Carles Hernández, Jaume Abella
2014	Misc	`conf`	Parallel many-core avionics systems. EMSOFT Milos Panic, Eduardo Quiñones, Pavel G. Zaykov, Carles Hernández, Jaume Abella, Francisco J. Cazorla
2013	J	`jnl`	Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2012	—	`conf`	Addressing Link Degradation in NoC-Based ULSI Designs. Euro-Par Workshops Carles Hernández, Federico Silla, José Duato
2012	B	`conf`	Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2012	J	`jnl`	On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2011	B	`conf`	A Distributed Switch Architecture for On-Chip Networks. ICPP Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2011	J	`jnl`	Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011	B	`conf`	Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. ICPP Carles Hernández, Federico Silla, José Duato
2011	J	`jnl`	Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Comput. Archit. Lett. Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011	J	`jnl`	Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. Int. J. Embed. Real Time Commun. Syst. Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi
2010	A	`conf`	A methodology for the characterization of process variation in NoC links. DATE Carles Hernández, Federico Silla, José Duato
2010	—	`conf`	Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2010	—	`conf`	Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. SoC Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi
2009	A	`conf`	A new mechanism to deal with process variability in NoC links. IPDPS Carles Hernández, Federico Silla, Vicente Santonja, José Duato
2009	—	`conf`	Yield-oriented evaluation methodology of network-on-chip routing implementations. SoC Samuel Rodrigo, Carles Hernández, José Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai