Carl Sechen - RankMe

96 papers A* 12A 25C 10Misc 3Journal 22Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. Aric Fowler, Mohammed Shayan, Mustafa M. Shihab, Thomas Broadfoot, Peter Beerel, Carl Sechen, Yiorgos Makris
2025	A	`conf`	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists. ITC Aric Fowler, Carl Sechen, Yiorgos Makris
2025	J	`jnl`	Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen
2024	Misc	`conf`	Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. VTS Apurva Jain, Thomas Broadfoot, Carl Sechen, Yiorgos Makris
2023	A	`conf`	Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. DATE Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen
2020	Misc	`conf`	ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. VTS Mustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris
2020	A	`conf`	An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. DATE Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2020	C	`conf`	CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. ISCAS Mustafa M. Shihab, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Jingxiang Tian, William Swartz, Carl Sechen, Yiorgos Makris
2020	C	`conf`	Optimal Standard Cell Library Composition for 7nm. ISCAS Vibhav Kumarswami Salimath, Carl Sechen
2019	A	`conf`	Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. DATE Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer, Carl Sechen, Yiorgos Makris
2019	—	`conf`	Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. FPT Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2019	—	`conf`	Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. ACM Great Lakes Symposium on VLSI Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
2019	A*	`conf`	Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
2017	J	`jnl`	A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2. IEEE J. Solid State Circuits Meisam Heidarpour Roshan, Samira Zaliasl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Amanpreet Singh, Sudhakar Pamarti, Nicholas Miller, Joseph C. Doll, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
2017	A	`conf`	A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. DATE Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen
2017	—	`conf`	Are standalone gate size and VT optimization tools useful? CCECE Anitha Kumari Yella, Gunturi Srivatsa, Carl Sechen
2017	—	`conf`	On designing optimal camouflaged layouts. HOST Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran
2016	—	`conf`	11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. ISSCC Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
2015	J	`jnl`	A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. Circuits Syst. Signal Process. Zhao Wang, Xiao He, Carl Sechen
2013	J	`jnl`	Library-Based Cell-Size Selection Using Extended Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammad Rahman, Hiran Tennakoon, Carl Sechen
2013	A	`conf`	Low-voltage low-overhead asynchronous logic. ISLPED Akshay Sridharan, Carl Sechen, Roozbeh Jafari
2012	A	`conf`	Post-synthesis leakage power minimization. DATE Mohammad Rahman, Carl Sechen
2011	—	`conf`	Power efficient partial product compression. ACM Great Lakes Symposium on VLSI Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen
2011	A	`conf`	Power reduction via near-optimal library-based cell-size selection. DATE Mohammad Rahman, Hiran Tennakoon, Carl Sechen
2011	A*	`conf`	Power reduction via separate synthesis and physical libraries. DAC Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen
2008	J	`jnl`	Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiran Tennakoon, Carl Sechen
2007	C	`conf`	Post-layout comparison of high performance 64b static adders in energy-delay space. ICCD Sheng Sun, Carl Sechen
2006	—	`conf`	A 64b adder using self-calibrating differential output prediction logic. ISSCC Kian Haur Chong, Larry McMurchie, Carl Sechen
2006	C	`conf`	Post-layout energy-delay analysis of parallel multipliers. ISCAS Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen
2005	—	`conf`	409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. ISVLSI Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen
2005	—	`conf`	A high throughput divider implementation. CICC Xinyu Guo, Carl Sechen
2005	—	`conf`	Efficient Post-layout Power-Delay Curve Generation. PATMOS Miodrag Vujkovic, David Wadkins, Carl Sechen
2005	A*	`conf`	Efficient and accurate gate sizing with piecewise convex delay models. DAC Hiran Tennakoon, Carl Sechen
2005	—	`conf`	High Speed Redundant Adder and Divider in Output Prediction Logic. ISVLSI Xinyu Guo, Carl Sechen
2004	—	`conf`	A high performance CMOS programmable logic core. CICC Yi Han, Larry McMurchie, Carl Sechen
2004	A*	`conf`	Efficient timing closure without timing driven placement and routing. DAC Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen
2003	—	`conf`	A low power delayed-clocks generation and distribution system. ISCAS (5) Su Kio, Kian Haur Chong, Carl Sechen
2003	J	`jnl`	Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jovanka Ciric, Carl Sechen
2003	A*	`conf`	Libraries: lifejacket or straitjacket. DAC Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar
2002	A	`conf`	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD Hiran Tennakoon, Carl Sechen
2002	J	`jnl`	Locally clocked pipelines and dynamic logic. IEEE Trans. Very Large Scale Integr. Syst. Gregg N. Hoyer, Gin Yee, Carl Sechen
2002	—	`conf`	Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS Miodrag Vujkovic, Carl Sechen
2002	A	`conf`	Optimized power-delay curve generation for standard cell ICs. ICCAD Miodrag Vujkovic, Carl Sechen
2002	A	`conf`	WTA: waveform-based timing analysis for deep submicron circuits. ICCAD Larry McMurchie, Carl Sechen
2001	—	`conf`	A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ARVLSI Sheng Sun, Larry McMurchie, Carl Sechen
2001	A	`conf`	Automatic datapath tile placement and routing. DATE Tatjana Serdar, Carl Sechen
2001	A	`conf`	Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD Jovanka Ciric, Carl Sechen
2001	A*	`conf`	Panel: (When) Will FPGAs Kill ASICs? DAC Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
2001	J	`jnl`	Timing- and crosstalk-driven area routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
2000	—	`conf`	A locally-clocked dynamic logic serial/parallel multiplier. CICC Gregg N. Hoyer, Carl Sechen
2000	—	`conf`	An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen
2000	J	`jnl`	Clock-delayed domino for dynamic circuit design. IEEE Trans. Very Large Scale Integr. Syst. Gin Yee, Carl Sechen
2000	A	`conf`	Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE Jovanka Ciric, Gin Yee, Carl Sechen
2000	C	`conf`	Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
1999	J	`jnl`	A gridless multilayer router for standard cell circuits using CTMcells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Ping Tseng, Carl Sechen
1999	A	`conf`	AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. ICCAD Tatjana Serdar, Carl Sechen
1999	C	`conf`	Design and Synthesis of Monotonic Circuits. ICCD Tyler Thorp, Gin Yee, Carl Sechen
1999	J	`jnl`	Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Le-Chin Eugene Liu, Carl Sechen
1999	J	`jnl`	Multilayer pin assignment for macro cell circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Le-Chin Eugene Liu, Carl Sechen
1998	—	`conf`	Chip-level area routing. ISPD Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen
1998	A	`conf`	Domino logic synthesis using complex static gates. ICCAD Tyler Thorp, Gin Yee, Carl Sechen
1998	A*	`conf`	Timing and Crosstalk Driven Area Routing. DAC Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
1997	—	`conf`	A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC Hsiao-Ping Tseng, Carl Sechen
1997	J	`jnl`	A parallel standard cell placement algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wern-Jieh Sun, Carl Sechen
1997	J	`jnl`	Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qicheng Yu, Carl Sechen
1997	—	`conf`	Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC Le-Chin Eugene Liu, Carl Sechen
1997	A*	`conf`	The Future of Custom Cell Generation in Physical Synthesis. DAC Martin Lefebvre, David Marple, Carl Sechen
1996	J	`jnl`	A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
1996	J	`jnl`	A Timing-Driven Partitioning System for Multiple FPGAs. VLSI Design Kalapi Roy-Neogi, Carl Sechen
1996	C	`conf`	Clock-Delayed Domino for Adder and Combinational Logic Desig. ICCD Gin Yee, Carl Sechen
1996	J	`jnl`	Generation of colour-constrained spanning trees with application in symbolic circuit analysis. Int. J. Circuit Theory Appl. Qicheng Yu, Carl Sechen
1996	C	`conf`	Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ICCD Bingzhong Guan, Carl Sechen
1995	A*	`conf`	A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. DAC Ted Stanion, Carl Sechen
1995	C	`conf`	Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. ISCAS Jer-Jaw Hsu, Carl Sechen
1995	J	`jnl`	An efficient method for generating exhaustive test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ted Stanion, Debashis Bhattacharya, Carl Sechen
1995	C	`conf`	Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS Qicheng Yu, Carl Sechen
1995	J	`jnl`	Efficient and effective placement for very large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wern-Jieh Sun, Carl Sechen
1995	A	`conf`	Multiple FPGA Partitioning with Performance Optimization. FPGA Kalapi Roy-Neogi, Carl Sechen
1995	—	`conf`	Quasi-algebraic decompositions of switching functions. ARVLSI Ted Stanion, Carl Sechen
1995	A*	`conf`	Timing Driven Placement for Large Standard Cell Circuits. DAC William Swartz, Carl Sechen
1994	Misc	`conf`	A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
1994	A	`conf`	A loosely coupled parallel algorithm for standard cell placement. ICCAD Wern-Jieh Sun, Carl Sechen
1994	A	`conf`	Approximate symbolic analysis of large analog integrated circuits. ICCAD Qicheng Yu, Carl Sechen
1994	J	`jnl`	Boolean division and factorization using binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ted Stanion, Carl Sechen
1994	—	`conf`	Generation of color-constrained spanning trees with application in symbolic circuit analysis. Great Lakes Symposium on VLSI Qicheng Yu, Carl Sechen
1993	A	`conf`	A new generalized row-based global router. ICCAD William Swartz, Carl Sechen
1993	A	`conf`	Efficient and effective placement for very large circuits. ICCAD Wern-Jieh Sun, Carl Sechen
1993	A	`conf`	Maximum projections of don't care conditions in a Boolean network. ICCAD Ted Stanion, Carl Sechen
1991	—	`conf`	A global router for sea-of-gates circuits. EURO-DAC Kai-Win Lee, Carl Sechen
1991	—	`conf`	Mickey: a macro cell global router. EURO-DAC Dahe Chen, Carl Sechen
1990	A	`conf`	New Algorithms for the Placement and Routing of Macro Cells. ICCAD William Swartz, Carl Sechen
1988	A	`conf`	A new global router for row-based layout. ICCAD Kai-Win Lee, Carl Sechen
1988	A	`conf`	An improved objective function for mincut circuit partitioning. ICCAD Carl Sechen, Dahe Chen
1988	A*	`conf`	Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. DAC Carl Sechen
1988	J	`jnl`	ThunderBird: a complete standard cell layout package. IEEE J. Solid State Circuits Carl Sechen, Douglas Braun, Alberto L. Sangiovanni-Vincentelli
1986	A*	`conf`	TimberWolf3.2: a new standard cell placement and global routing package. DAC Carl Sechen, Alberto L. Sangiovanni-Vincentelli