Carl Pixley - RankMe

51 papers A* 10A 9B 2C 4Misc 1Journal 15Unranked 9

Year	Rank	Type	Title / Venue / Authors
2009	A	`conf`	Solver technology for system-level to RTL equivalence checking. DATE Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley
2008	—	`conf`	Practical Considerations Concerning HL-to -RT Equivalence Checking. Haifa Verification Conference Carl Pixley
2007	A	`conf`	A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. DATE In-Ho Moon, Per Bjesse, Carl Pixley
2007	A*	`conf`	Memory Modeling in ESL-RTL Equivalence Checking. DAC Alfred Kölbl, Jerry R. Burch, Carl Pixley
2006	—	`book`	Constraint-based verification. Jun Yuan, Carl Pixley, Adnan Aziz
2006	J	`jnl`	Guest Editors' Introduction: The True State of the Art of ESL Design. IEEE Des. Test Comput. Sandeep K. Shukla, Carl Pixley, Gary Smith
2006	—	`conf`	Panel: Assertion-Based Verification -What's the Big Deal? HLDVT Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley
2006	—	`conf`	Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. HLDVT In-Ho Moon, Per Bjesse, Carl Pixley
2005	J	`jnl`	Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. Int. J. Parallel Program. Alfred Kölbl, Carl Pixley
2004	C	`conf`	Designers want proofs - but show me the money. MEMOCODE Carl Pixley, D. Meyers, S. McMaster, A. Chittor
2004	J	`jnl`	Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Des. Test Comput. Carl Pixley, Sharad Malik
2004	B	`conf`	Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. FMCAD In-Ho Moon, Carl Pixley
2004	J	`jnl`	Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin
2003	A	`conf`	A Framework for Constrained Functional Verification. ICCAD Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin
2003	A*	`conf`	Constraint synthesis for environment modeling in functional verification. DAC Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
2003	A*	`conf`	Formal verification - prove it or pitch it. DAC Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
2003	J	`jnl`	Panel Summaries. IEEE Des. Test Comput. Carl Pixley, Juan Antonio Carballo
2003	J	`jnl`	Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
2002	A	`conf`	Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
2002	B	`conf`	Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
2002	—	`conf`	Simplifying Constraint Solving in Random Simulation Generation. IWLS Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
2001	—	`conf`	Application of Formal Verification to Design Creation and Implementation. ISQED Noel R. Strader, Gérard Memmi, Carl Pixley
2001	—	`conf`	Experience with term level modeling and verification of the M*CORE HLDVT Shuvendu K. Lahiri, Carl Pixley, Ken Albin
2001	J	`jnl`	Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Des. Test Comput. Carl Pixley
2001	J	`jnl`	Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
2000	J	`jnl`	An Efficient Logic Equivalence Checker for Industrial Circuits. J. Electron. Test. Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho
2000	J	`jnl`	Automatic Vector Generation Using Constraints and Biasing. J. Electron. Test. Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
1999	Misc	`conf`	Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. PDPTA Carl Pixley, Kurt Shultz, Jun Yuan
1999	J	`jnl`	Model Checking: A Hardware Design Perspective. Int. J. Softw. Tools Technol. Transf. Carl Pixley, Vigyan Singhal
1999	A	`conf`	Modeling design constraints and biasing in simulation using BDDs. ICCAD Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
1998	A	`conf`	Approximate reachability don't cares for CTL model checking. ICCAD In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
1998	A*	`conf`	Design Constraints in Symbolic Model Checking. CAV Matt Kaufmann, Andrew Martin, Carl Pixley
1998	—	`conf`	Logic and Functional Verification in a Commercial Semiconductor Environment. ACSD Jainendra Kumar, Carl Pixley
1997	A*	`conf`	Formal Verification of FIRE: A Case Study. DAC Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley
1997	C	`conf`	Intertwined Development and Formal Verification of a 60x Bus Model. ICCD Matt Kaufmann, Carl Pixley
1996	A	`conf`	Commercial Design Verification: Methodology and Tools. ITC Carl Pixley, Noel R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen
1995	—	`conf`	Exploiting power-up delay for sequential optimization. EURO-DAC Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
1995	C	`conf`	Power-Up Delay for Retiming Digital Circuits. ISCAS Vigyan Singhal, Robert K. Brayton, Carl Pixley
1995	A*	`conf`	The Validity of Retiming Sequential Circuits. DAC Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
1994	J	`jnl`	Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
1994	A	`conf`	Multi-level synthesis for safe replaceability. ICCAD Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
1994	A*	`conf`	The Verifiacation Problem for Safe Replaceability. CAV Vigyan Singhal, Carl Pixley
1993	A*	`conf`	Minimum Length Synchronizing Sequences of Finite State Machine. DAC June-Kyung Rho, Fabio Somenzi, Carl Pixley
1993	J	`jnl`	Synchronizing sequences and symbolic traversal techniques in test generation. J. Electron. Test. Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley
1992	J	`jnl`	A theory and implementation of sequential hardware equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carl Pixley
1992	A*	`conf`	Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
1991	C	`conf`	Automatic Derivation of FSM Specification to Implementation Encoding. ICCD Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes
1991	A	`conf`	Calculating Resetability and Reset Sequences. ICCAD Carl Pixley, Gary Beihl
1990	—	`conf`	A Computation Theory and Implementation of Sequential Hardware Equivalence. CAV (DIMACS/AMS volume) Carl Pixley
1990	A*	`conf`	Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. CAV Carl Pixley
1988	J	`jnl`	An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. Distributed Comput. Carl Pixley