Carl Ebeling - RankMe

57 papers A* 3A 15B 9C 1Misc 4Journal 14Unranked 11

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Mapping Stencils on Coarse-grained Reconfigurable Spatial Architecture. CoRR Jesmin Jahan Tithi, Fabrizio Petrini, Hongbo Rong, Andrei Valentin, Carl Ebeling
2016	A	`conf`	Stratix™ 10 High Performance Routable Clock Networks. FPGA Carl Ebeling, Dana How, David M. Lewis, Herman Schmit
2012	B	`conf`	Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. FPL Robin Panda, Carl Ebeling, Scott Hauck
2012	Misc	`conf`	Hardware Acceleration of Short Read Mapping. FCCM Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo
2011	—	`conf`	Crunching Large Graphs with Commodity Processors. HotPar Jacob Nelson, Brandon Myers, A. H. Hunter, Preston Briggs, Luis Ceze, Carl Ebeling, Dan Grossman, Simon Kahan, Mark Oskin
2011	A	`conf`	Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. FPGA Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
2010	B	`conf`	Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. FPL Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
2009	A	`conf`	SPR: an architecture-adaptive CGRA mapping tool. FPGA Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
2009	B	`conf`	Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. FPL Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
2007	—	`conf`	Abstract Verilog: A Hardware Description Language for Novice Students. MSE Carl Ebeling, Brian French
2006	Misc	`conf`	A Type Architecture for Hybrid Micro-Parallel Computers. FCCM Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
2006	A	`conf`	A type architecture for hybrid micro-parallel computers. FPGA Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
2006	—	`conf`	Configurable Computing Platforms - Promises, Promises. ASAP Carl Ebeling
2006	J	`jnl`	PipeRoute: a pipelining-aware router for reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Akshay Sharma, Carl Ebeling, Scott Hauck
2006	B	`conf`	Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. FPL Allan Carroll, Carl Ebeling
2005	A	`conf`	Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). FPGA Akshay Sharma, Carl Ebeling, Scott Hauck
2005	B	`conf`	Architecture-Adaptive Routability-Driven Placement for FPGAs. FPL Akshay Sharma, Carl Ebeling, Scott Hauck
2004	A	`conf`	A compiled accelerator for biological cell signaling simulations. FPGA John F. Keane, Christopher Bradley, Carl Ebeling
2004	A	`conf`	Exploration of pipelined FPGA interconnect structures. FPGA Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
2004	J	`jnl`	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. IEEE Trans. Computers Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
2004	—	`conf`	QuickRoute: a fast routing algorithm for pipelined architectures. FPT Song Li, Carl Ebeling
2003	B	`conf`	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. FPL Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
2003	A	`conf`	PipeRoute: a pipelining-aware router for FPGAs. FPGA Akshay Sharma, Carl Ebeling, Scott Hauck
2001	B	`conf`	An Emulator for Exploring RaPiD Configurable Computing Architectures. FPL Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling
2000	J	`jnl`	Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
1999	—	`conf`	Architecture Design of Reconfigurable Pipelined Datapaths. ARVLSI Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling
1998	J	`jnl`	Mesh routing topologies for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. Scott Hauck, Gaetano Borriello, Carl Ebeling
1998	Misc	`conf`	Specifying and Compiling Applications for RaPiD. FCCM Darren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling
1998	A	`conf`	Using precomputation in architecture and logic resynthesis. ICCAD Soha Hassoun, Carl Ebeling
1997	—	`conf`	ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing. PCRCW Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
1997	—	`conf`	Configurable computing: the catalyst for high-performance architectures. ASAP Carl Ebeling, Darren C. Cronquist, Paul Franklin
1997	Misc	`conf`	Mapping applications to the RaPiD configurable architecture. FCCM Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg
1997	A	`ed.`	Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997 FPGA Carl Ebeling
1997	J	`jnl`	Seeking Solutions in Configurable Computing. Computer William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
1997	—	`conf`	Whither Configurable Computing? HICSS (1) Carl Ebeling
1996	A*	`conf`	Architectural Retiming: Pipelining Latency-Constrained Circuts. DAC Soha Hassoun, Carl Ebeling
1996	A	`ed.`	Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996 FPGA Jonathan Rose, Carl Ebeling
1996	B	`conf`	RaPiD - Reconfigurable Pipelined Datapath. FPL Carl Ebeling, Darren C. Cronquist, Paul Franklin
1995	—	`conf`	On the performance of level-clocked circuits. ARVLSI Carl Ebeling, Brian Lockyear
1995	A	`conf`	PathFinder: A Negotiation-based Performance-driven Router for FPGAs. FPGA Larry McMurchie, Carl Ebeling
1995	J	`jnl`	Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
1995	J	`jnl`	The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
1994	J	`jnl`	An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
1994	—	`conf`	CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks. PCRCW Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
1994	C	`conf`	Mesh Routing Topologies for Multi-FPGA Systems. ICCD Scott Hauck, Gaetano Borriello, Carl Ebeling
1994	J	`jnl`	Optimal retiming of level-clocked circuits using symmetric clock schedules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brian Lockyear, Carl Ebeling
1993	A*	`conf`	SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. DAC Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather
1993	—	`conf`	The chaos router chip: design and implementation of an adaptive router. VLSI Kevin Bolding, Sen-Ching S. Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille
1993	A	`conf`	The practical application of retiming to the design of high-performance systems. ICCAD Brian Lockyear, Carl Ebeling
1992	B	`conf`	MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
1990	J	`jnl`	Measuring the Performance Potential of Chess Programs. Artif. Intell. Hans J. Berliner, Gordon Goetsch, Murray Campbell, Carl Ebeling
1989	J	`jnl`	Apex: two architectures for generating parametric curves and surfaces. Vis. Comput. Tony DeRose, Mary L. Bailey, Bill Barnard, Robert Cypher, David Dobrikin, Carl Ebeling, Smaragda Konstantinidou, Larry McMurchie, Haim Mizrahi, Bill Yost
1989	J	`jnl`	Pattern Knowledge and Search: The SUPREM Architecture. Artif. Intell. Hans J. Berliner, Carl Ebeling
1989	A	`conf`	WireLisp: combining graphics and procedures in a circuit specification language. ICCAD Carl Ebeling, Zhanbing Wu
1988	A	`conf`	GeminiII: a second generation layout validation program. ICCAD Carl Ebeling
1986	J	`jnl`	The SUPREM Architecture: A New Intelligent Paradigm. Artif. Intell. Hans J. Berliner, Carl Ebeling
1984	A*	`conf`	The Design and Implementation of a VLSI Chess Move Generator. ISCA Carl Ebeling, Andrew J. Palay