Carl-Johan H. Seger

54 papers A* 12A 4B 6C 6Journal 15Unranked 9
YearRankTypeTitle / Venue / Authors
2024 C conf
Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor.
MEMOCODE
Jeremy Pope, Carl-Johan H. Seger, Henrik Valter
2023 C conf
Bifröst: Creating Hardware With Building Blocks.
FDL
Jeremy Pope, Carl-Johan H. Seger
2021 B conf
Formal Verification of Complex Data Paths: An Industrial Experience.
FM
Carl-Johan H. Seger
2020 C conf
Cephalopode: A custom processor aimed at functional language execution for IoT devices.
MEMOCODE
Jeremy Pope, Jules Saget, Carl-Johan H. Seger
2020 C conf
Stately: An FSM Design Tool.
MEMOCODE
Jeremy Pope, Jules Saget, Carl-Johan H. Seger
2017 J jnl
Symbolic trajectory evaluation for word-level verification: theory and implementation.
Formal Methods Syst. Des.
Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry
2015 — conf
Word-Level Symbolic Trajectory Evaluation.
CAV (2)
Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry
2015 J jnl
Word-level Symbolic Trajectory Evaluation.
CoRR
Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry
2007 B conf
Automatic Abstraction in Symbolic Trajectory Evaluation.
FMCAD
Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger
2005 J jnl
An industrially effective environment for formal hardware verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme
2004 A* conf
Compositional Specification and Model Checking in GSTE.
CAV
Jin Yang, Carl-Johan H. Seger
2003 J jnl
Introduction to generalized symbolic trajectory evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Jin Yang, Carl-Johan H. Seger
2002 B conf
Generalized Symbolic Trajectory Evaluation - Abstraction in Action.
FMCAD
Jin Yang, Carl-Johan H. Seger
2001 A* conf
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV
John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
2001 C conf
Introduction to Generalized Symbolic Trajectory Evaluation.
ICCD
Jin Yang, Carl-Johan H. Seger
2001 J jnl
Practical Formal Verification in Microprocessor Design.
IEEE Des. Test Comput.
Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham
2000 B conf
A Methodology for Large-Scale Hardware Verification.
FMCAD
Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger
2000 A conf
Combining functional programming and hardware verification (abstract of invited talk).
ICFP
Carl-Johan H. Seger
2000 A conf
Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice.
CADE
Carl-Johan H. Seger
2000 A* conf
Formal verification of iterative algorithms in microprocessors.
DAC
Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger
1999 — conf
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving.
TPHOLs
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
1999 J jnl
Model Checking Lattices: Using and reasoning about information orders for abstraction.
Log. J. IGPL
Scott Hazelhurst, Carl-Johan H. Seger
1999 A* conf
Parametric Representations of Boolean Constraints.
DAC
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
1998 A* conf
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment.
DAC
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
1998 B conf
Formal Methods in CAD from an Industrial Perspective (abstract).
FMCAD
Carl-Johan H. Seger
1998 — conf
From lattices to practical formal hardware verification.
PROCOMET
Carl-Johan H. Seger
1997 — conf
Symbolic Trajectory Evaluation.
Formal Hardware Verification
Scott Hazelhurst, Carl-Johan H. Seger
1996 B conf
Self-Consistency Checking.
FMCAD
Robert B. Jones, Carl-Johan H. Seger, David L. Dill
1995 J jnl
A simple theorem prover based on symbolic trajectory evaluation and BDD's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Scott Hazelhurst, Carl-Johan H. Seger
1995 — book
Asynchronous Circuits.
Janusz A. Brzozowski, Carl-Johan H. Seger
1995 J jnl
Automatic Verification of Asynchronous Circuits.
IEEE Des. Test Comput.
Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
1995 J jnl
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories.
Formal Methods Syst. Des.
Carl-Johan H. Seger, Randal E. Bryant
1995 A conf
The formal verification of a pipelined double-precision IEEE floating-point multiplier.
ICCAD
Mark D. Aagaard, Carl-Johan H. Seger
1994 C conf
Automatic Verification of Refinement.
ICCD
Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
1994 A* conf
Composing Symbolic Trajectory Evaluation Results.
CAV
Scott Hazelhurst, Carl-Johan H. Seger
1994 — conf
Digital Circuit Verification Using Partially-Ordered State Models.
ISMVL
Carl-Johan H. Seger, Randal E. Bryant
1994 J jnl
Generalized Ternary Simulation of Sequential Circuits.
RAIRO Theor. Informatics Appl.
Carl-Johan H. Seger, Janusz A. Brzozowski
1994 — ed.
Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings
HUG
Jeffrey J. Joyce, Carl-Johan H. Seger
1994 A* conf
The Completeness of a Hardware Inference System.
CAV
Zheng Zhu, Carl-Johan H. Seger
1993 — conf
From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.
HUG
Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger
1993 A* conf
Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving.
DAC
Jeffrey J. Joyce, Carl-Johan H. Seger
1993 — conf
The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover.
HUG
Jeffrey J. Joyce, Carl-Johan H. Seger
1993 — conf
Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment.
HUG
Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger
1991 A* conf
A Two-Level Formal Verification Methodology using HOL and COSMOS.
CAV
Carl-Johan H. Seger, Jeffrey J. Joyce
1991 A* conf
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation.
DAC
Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger
1991 J jnl
On the Existence of Speed-Independent Circuits.
Theor. Comput. Sci.
Carl-Johan H. Seger
1990 A* conf
Formal Verification of Digital Circuits Using Symbolic Ternary System Models.
CAV
Randal E. Bryant, Carl-Johan H. Seger
1990 — conf
Formal Verification of Digital Circuits Using Symbolic Ternary System Models.
CAV (DIMACS/AMS volume)
Randal E. Bryant, Carl-Johan H. Seger
1989 A conf
A bounded delay race model.
ICCAD
Carl-Johan H. Seger
1989 J jnl
A unified framework for race analysis of asynchronous networks.
J. ACM
Janusz A. Brzozowski, Carl-Johan H. Seger
1988 J jnl
An Optimistic Ternary Simulation of Gate Races.
Theor. Comput. Sci.
Carl-Johan H. Seger, Janusz A. Brzozowski
1987 J jnl
A Characterization of Ternary Simulation of Gate Networks.
IEEE Trans. Computers
Janusz A. Brzozowski, Carl-Johan H. Seger
1986 A* conf
Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary).
ICALP
Janusz A. Brzozowski, Carl-Johan H. Seger
1986 J jnl
Robust Storage Structures for Crash Recovery.
IEEE Trans. Computers
David J. Taylor, Carl-Johan H. Seger