Can Sitik

15 papers C 4Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2019 — conf
Low Voltage Clock Tree Synthesis with Local Gate Clusters.
ACM Great Lakes Symposium on VLSI
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
2019 J jnl
SLECTS: Slew-Driven Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
2016 J jnl
Design Methodology for Voltage-Scaled Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
2016 C conf
Exploiting useful skew in gated low voltage clock trees.
ISCAS
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015 — conf
A Novel Static D-Flip-Flop Topology for Low Swing Clocking.
ACM Great Lakes Symposium on VLSI
Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015 — conf
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.
ACM Great Lakes Symposium on VLSI
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015 C conf
Enhanced level shifter for multi-voltage operation.
ISCAS
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
2015 J jnl
FinFET-Based Low-Swing Clocking.
ACM J. Emerg. Technol. Comput. Syst.
Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin
2014 — conf
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.
ISVLSI
Can Sitik, Leo Filippini, Emre Salman, Baris Taskin
2014 J jnl
Iterative skew minimization for low swing clocks.
Integr.
Can Sitik, Baris Taskin
2014 C conf
Timing characterization of clock buffers for clock tree synthesis.
ICCD
Can Sitik, Scott Lerner, Baris Taskin
2013 — conf
A microcontroller-based embedded system design course with PSoC3.
MSE
Can Sitik, Prawat Nagvajara, Baris Taskin
2013 — conf
Multi-corner multi-voltage domain clock mesh design.
ACM Great Lakes Symposium on VLSI
Can Sitik, Baris Taskin
2013 — conf
Skew-bounded low swing clock tree optimization.
ACM Great Lakes Symposium on VLSI
Can Sitik, Baris Taskin
2012 C conf
Multi-voltage domain clock mesh design.
ICCD
Can Sitik, Baris Taskin