| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2019 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2017 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2017 | A* | conf |
DAC
|
| 2017 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2016 | Misc | conf |
FCCM
|
| 2016 | J | jnl |
IEEE Trans. Multi Scale Comput. Syst.
|
| 2016 | J | jnl |
IEEE Des. Test
|
| 2016 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2016 | A | conf |
ISLPED
|
| 2015 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2014 | J | jnl |
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
Integr.
|
| 2014 | — | conf |
ISPD
|
| 2014 | A | conf |
ISLPED
|
| 2013 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2013 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2013 | — | conf |
3DIC
|
| 2013 | — | conf |
DFTS
|