Caaliph Andriamisaina

16 papers A 3C 2Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2025 C conf
Extending Instruction Set Simulators with ML-based Performance Models: Application to QEMU.
RSP
Fatma Jebali, Caaliph Andriamisaina
2025 A conf
Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN.
DATE
Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack
2024 C conf
A Methodology for Fast and Efficient ML-Based Power Modeling.
ICCD
Caaliph Andriamisaina, Kods Trabelsi, Pierre-Guillaume Le Guay
2019 J jnl
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing.
IEEE J. Solid State Circuits
Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton
2019 — conf
Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design.
DASIP
Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux
2018 — conf
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing.
VLSI Circuits
Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq
2014 J jnl
HARS: A hardware-assisted runtime software for embedded many-core architectures.
ACM Trans. Embed. Comput. Syst.
Yves Lhuillier, Maroun Ojail, Alexandre Guerre, Jean-Marc Philippe, Karim Ben Chehida, Farhat Thabet, Caaliph Andriamisaina, Chafic Jaber, Raphaël David
2013 A conf
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture.
DATE
Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David
2010 J jnl
High-Level Synthesis for Designing Multimode Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
2008 J jnl
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.
Tech. Sci. Informatiques
Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina
2007 A conf
A design flow dedicated to multi-mode architectures for DSP applications.
ICCAD
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
2007 — conf
Synthesis of Multimode digital signal processing systems.
AHS
Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy
2006 — conf
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems.
SoCC
Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau
2006 — conf
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.
SiPS
Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau
2006 J jnl
Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques.
Tech. Sci. Informatiques
Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou
2005 — conf
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.
ERSA
Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier