C. Y. Roger Chen

73 papers A* 8A 6B 2C 9Misc 1Journal 26Unranked 20

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	CWcollab: A Context-Aware Web-Based Collaborative Multimedia System. CoRR Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu
2022	J	`jnl`	CWcollab: Presenting multimedia with web-based context-aware collaboration. Entertain. Comput. Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu
2021	—	`conf`	CWcollab: A Context-Aware Web-Based Collaborative Multimedia System. ICC Chunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu
2016	J	`jnl`	Transistor and pin reordering for leakage reduction in CMOS circuits. Microelectron. J. Jae Woong Chun, C. Y. Roger Chen
2015	—	`conf`	Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model. ACM Great Lakes Symposium on VLSI Jiani Xie, C. Y. Roger Chen
2012	—	`conf`	A tool to generate models based on behavioral IBIS models. MWSCAS B. S. Deepaksubramanyan, C. Y. Roger Chen, Adrian Nunez
2008	C	`conf`	Modeling and reduction of complex timing constraints in high performance digital circuits. ICCD Veerapaneni Nagbhushan, C. Y. Roger Chen
2007	C	`conf`	A technique for selecting CMOS transistor orders. ICCD Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen
2007	C	`conf`	Algorithms to simplify multi-clock/edge timing constraints. ICCD Veerapaneni Nagbhushan, C. Y. Roger Chen
2007	C	`conf`	An efficient gate delay model for VLSI design. ICCD Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen
2003	—	`conf`	A novel ultra-fast heuristic for VLSI CAD steiner trees. ACM Great Lakes Symposium on VLSI Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
2003	—	`conf`	Detailed Placement with Net Length Constraints. IWSOC Bill Halpin, Naresh Sehgal, C. Y. Roger Chen
2001	A*	`conf`	Timing Driven Placement using Physical Net Constraints. DAC Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
2000	—	`conf`	A novel technique for sea of gates global routing. ACM Great Lakes Symposium on VLSI Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
2000	—	`conf`	A sensitivity based placer for standard cells. ACM Great Lakes Symposium on VLSI Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
2000	J	`jnl`	Methodologies for Designing Video Servers. IEEE Trans. Multim. Dikran S. Meliksetian, Frank Feng-Kuo Yu, C. Y. Roger Chen
2000	J	`jnl`	Partitionable multistage interconnection networks. Part 2: Task migration schemes. Telecommun. Syst. Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen
1999	J	`jnl`	Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology. Discret. Appl. Math. Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1998	J	`jnl`	Partitionable multistage interconnection networks. Part 1: Dynamic subcube compaction. Telecommun. Syst. Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen
1998	Misc	`conf`	Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. VLSI Design Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
1997	—	`conf`	Smoothing Algorithms for the Delivery of Compressed Video. ICC (3) Tacettin Kiprulu, Dikran S. Meliksetian, C. Y. Roger Chen
1996	—	`conf`	Transistor Chaining in CMOS Leaf Cells of Planar Topology. Great Lakes Symposium on VLSI Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1995	J	`jnl`	A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. IEEE/ACM Trans. Netw. C. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad
1995	J	`jnl`	A pin permutation algorithm for improving over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. C. Y. Roger Chen, Cliff Yungchin Hou
1995	J	`jnl`	A preprocessor for improving channel routing hierarchical pin permutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson
1995	J	`jnl`	A queueing analysis of the performance of DQDB. IEEE/ACM Trans. Netw. C. Y. Roger Chen, Georges A. Makhoul, Dikran S. Meliksetian
1995	J	`jnl`	Design of a Multimedia Object-Oriented DBMS. Multim. Syst. C. Y. Roger Chen, Dikran S. Meliksetian, M. C. Chang, L. J. Liu
1995	J	`jnl`	Dual Eulerian Properties of Plane Multigraphs. SIAM J. Discret. Math. Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
1995	J	`jnl`	LILA: layout generation for iterative logic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson
1995	J	`jnl`	Special Issue on Multimedia Processing and Technology. J. Parallel Distributed Comput. Arif Ghafoor, C. Y. Roger Chen
1995	C	`conf`	Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs. ISCAS Calvin J. A. Hsia, C. Y. Roger Chen
1994	C	`conf`	A High Performance General Purpose Multi-Point Signal Router. ISCAS Naresh Kumar Seghal, C. Y. Roger Chen, John M. Acken
1994	—	`conf`	A gridless multi-layer area router. Great Lakes Symposium on VLSI Naresh Sehgal, C. Y. Roger Chen, John M. Acken
1994	—	`conf`	A new technique for exploiting regularity in data path synthesis. EURO-DAC C. Y. Roger Chen, Mohammed Aloqeely
1994	J	`jnl`	An analytical model for partially blocking finite-buffered switching networks. IEEE/ACM Trans. Netw. James V. Luciani, C. Y. Roger Chen
1994	A	`conf`	An object-oriented cell library manager. ICCAD Naresh Sehgal, C. Y. Roger Chen, John M. Acken
1994	C	`conf`	Efficent Boolean Matching Algorithm for Cell Libraries. ICCD Qinghong Wu, C. Y. Roger Chen, John M. Acken
1994	J	`jnl`	Multimedia Object Modeling and Storage Allocation Strategies. J. Intell. Inf. Syst. Kingsley C. Nwosu, C. Y. Roger Chen, P. Bruce Berra
1994	J	`jnl`	Optimal algorithms for bubble sort based non-Manhattan channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh
1994	B	`conf`	Performance Evaluation of HIPPI Interconnection System Using a Camp-On Strategy. LCN Abdulaziz S. Mazyad, C. Y. Roger Chen
1994	J	`jnl`	Performance analysis of single-buffered multistage interconnection networks. IEEE Trans. Commun. Shuo-Hsien Hsiao, C. Y. Roger Chen
1994	A*	`conf`	Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms. DAC Mohammed Aloqeely, C. Y. Roger Chen
1994	—	`conf`	Synthesis of Application-Specific Multiprocessor Systems. EDAC-ETC-EUROASIC Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen
1993	A*	`conf`	A Markov-Modulated Bernoulli Process Approximation for the Analysis of Banyan Networks. SIGMETRICS Dikran S. Meliksetian, C. Y. Roger Chen
1993	—	`conf`	A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection Networks. IPPS Shuo-Hsien Hsiao, C. Y. Roger Chen
1993	C	`conf`	Modeling and Storage Allocation Strategies for Homogeneous Parallel Access Storage Devices in Real Time Multimedia Information Processing. ICCI C. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra
1993	B	`conf`	Multimedia object modelling and storage allocation strategies for heterogeneous parallel access storage devices in real time multimedia computing systems. COMPSAC C. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra
1993	J	`jnl`	Optimal Routing Algorithm and the Diameter of the Cube-Connected Cycles. IEEE Trans. Parallel Distributed Syst. Dikran S. Meliksetian, C. Y. Roger Chen
1993	A*	`conf`	Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. DAC Bradley S. Carlson, C. Y. Roger Chen
1993	—	`ed.`	Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume I: Architecture. ICPP (1) C. Y. Roger Chen, P. Bruce Berra
1992	A*	`conf`	A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing. DAC Cliff Yungchin Hou, C. Y. Roger Chen
1992	—	`conf`	A heuristic for data path synthesis using multiport memories. Great Lakes Symposium on VLSI Imtiaz Ahmad, C. Y. Roger Chen
1992	J	`jnl`	From logic to symbolic layout for gate matrix. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Uminder Singh, C. Y. Roger Chen
1992	A	`conf`	Issues in Networking and Data Management of Distributed Multimedia Systems. HPDC P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Thomas D. C. Little
1992	A*	`conf`	Performance Analysis of Communications in Static Interconnection Networks. SIGMETRICS Dikran S. Meliksetian, C. Y. Roger Chen
1992	J	`jnl`	Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. IEEE Trans. Parallel Distributed Syst. Shuo-Hsien Hsiao, C. Y. Roger Chen
1992	—	`conf`	The Signal Flow Model: A novel Data Driven Approach to Parallel Processing. ICPP (1) Muhammad F. Mudawwar, C. Y. Roger Chen
1991	A	`conf`	A Hierarchical Methodology to Improve Channel Routing by Pin Permutation. ICCAD Cliff Yungchin Hou, C. Y. Roger Chen
1991	J	`jnl`	A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. C. Y. Roger Chen, Michael Z. Moricz
1991	A*	`conf`	Datapath Scheduling for Two-Level Pipelining. DAC C. Y. Roger Chen, Michael Z. Moricz
1991	J	`jnl`	Multimedia Synchronization. IEEE Data Eng. Bull. Thomas D. C. Little, C. Y. Roger Chen, C. S. Chang, P. Bruce Berra
1991	J	`jnl`	Optimal cell generation for dual independent layout styles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh
1991	—	`conf`	Performance analysis of single-buffered multistage interconnection networks. SPDP Shuo-Hsien Hsiao, C. Y. Roger Chen
1991	A	`conf`	Post-Processor for Data Path Synthesis Using Multiport Memories. ICCAD Imtiaz Ahmad, C. Y. Roger Chen
1990	A*	`conf`	A Transistor Reordering Technique for Gate Matrix Layout. DAC Uminder Singh, C. Y. Roger Chen
1990	J	`jnl`	Architecture for distributed multimedia database systems. Comput. Commun. P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Chin Chung Lin, Thomas D. C. Little, Donghoon Shin
1990	—	`conf`	Communication Aspects of the Cube Connected Cycles. ICPP (1) Dikran S. Meliksetian, C. Y. Roger Chen
1990	—	`conf`	Embedding Networks with Ring Connections in Hypercube Machines. ICPP (3) C. Y. Roger Chen, Yeh-Ching Chung
1990	—	`conf`	Permutation Capability of Multistage Interconnection Networks. ICPP (1) Calvin J. A. Hsia, C. Y. Roger Chen
1989	C	`conf`	On a class of (2n-1)-stage rearrangeable interconnection networks. ICCD Calvin J. A. Hsia, C. Y. Roger Chen
1988	A	`conf`	A new algorithm for CMOS gate matrix layout. ICCAD C. Y. Roger Chen, Cliff Yungchin Hou
1988	A	`conf`	A new layout optimization methodology for CMOS complex gates. ICCAD C. Y. Roger Chen, Cliff Yungchin Hou
1988	—	`conf`	TOBOL - a new methodology for the top-to-bottom level hardware description in VLSI design-automation systems. ICCL C. Y. Roger Chen