C. P. Ravikumar

116 papers A* 1A 9B 4C 1Misc 40Journal 41Unranked 20
YearRankTypeTitle / Venue / Authors
2024 — conf
Predictive Modeling for Engineering Student Performance Forecasting and Course Correction.
TALE
C. P. Ravikumar, N. Sasikala
2020 C conf
Industrial Practices in Low-Power Robust Design.
IOLTS
C. P. Ravikumar
2018 J jnl
Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security.
J. Low Power Electron.
Ananya Ravikumar, C. P. Ravikumar
2016 J jnl
Smart and Fault-Tolerant LED-Based Street Lamps.
J. Low Power Electron.
C. P. Ravikumar
2013 J jnl
Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation
CoRR
Namita Sharma, Vineet Sahula, C. P. Ravikumar
2012 J jnl
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.
ACM Trans. Embed. Comput. Syst.
T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar
2008 J jnl
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.
J. Low Power Electron.
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2008 Misc conf
Memory Architecture Exploration Framework for Cache Based Embedded SOC.
VLSI Design
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
2008 Misc conf
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.
VLSI Design
Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan
2008 A ed.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008
ISLPED
Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle
2008 A conf
Test Strategies for Low Power Devices.
DATE
C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen
2008 J jnl
Test Strategies for Low-Power Devices.
J. Low Power Electron.
C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen
2007 J jnl
A critical-path-aware partial gating approach for test power reduction.
ACM Trans. Design Autom. Electr. Syst.
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
2007 A conf
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.
ITC
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007 J jnl
Conference Reports.
IEEE Des. Test Comput.
C. P. Ravikumar, Jari Nurmi
2007 Misc conf
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
VTS
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007 A conf
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
DATE
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007 J jnl
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler
2007 J jnl
Low-Power Hierarchical Scan Test for Multiple Clock Domains.
J. Low Power Electron.
Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
2007 Misc conf
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.
VLSI Design
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
2007 — conf
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.
ASP-DAC
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
2007 — conf
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.
ATS
Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
2007 A conf
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.
ITC
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2007 Misc conf
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.
VLSI Design
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007 J jnl
Variation-Tolerant, Power-Safe Pattern Generation.
IEEE Des. Test Comput.
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2006 J jnl
Conference Reports.
IEEE Des. Test Comput.
Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
2006 J jnl
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.
J. Low Power Electron.
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2005 Misc conf
A Framework for Distributed and Hierarchical Design-for-Test.
VLSI Design
C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
2005 A conf
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.
ITC
Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy
2005 Misc conf
At-Speed Transition Fault Testing With Low Speed Scan Enable.
VTS
Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
2005 A conf
Enhanced launch-off-capture transition fault testing.
ITC
Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar
2005 — conf
Partial Gating Optimization for Power Reduction During Test Application.
Asian Test Symposium
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
2004 A conf
A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
ITC
C. P. Ravikumar, Graham Hetherington
2004 J jnl
A self-checking signature scheme for checking backdoor security attacks in Internet.
J. High Speed Networks
Mohammed Fadle Abdulla, C. P. Ravikumar
2004 Misc conf
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.
VLSI Design
Aman Kokrady, C. P. Ravikumar
2004 Misc conf
Multiprocessor Architectures for Embedded System-on-chip Applications.
VLSI Design
C. P. Ravikumar
2003 Misc conf
Mutual Testing based on Wavelet Transforms.
VLSI Design
C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra
2003 Misc conf
Optimal Code and Data Layout in Embedded Systems.
VLSI Design
T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar
2003 A conf
Static Verification of Test Vectors for IR Drop Failure.
ICCAD
Aman Kokrady, C. P. Ravikumar
2002 — conf
An Evolutionary Scheme for Cosynthesis of Real-Time Systems.
ASP-DAC/VLSI Design
Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri
2002 — conf
Divide-and-Conquer IDDQ Testing for Core-Based System Chips.
ASP-DAC/VLSI Design
C. P. Ravikumar, Rahul Kumar
2002 — conf
Improvement of ASIC Design Processes.
ASP-DAC/VLSI Design
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
2002 — conf
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.
ASP-DAC/VLSI Design
Rahul Kumar, C. P. Ravikumar
2002 — conf
Measuring the Quality of Web Search Results.
JCIS
Mirza Mohd. Sufyan Beg, C. P. Ravikumar
2001 J jnl
Distributed Fault Simulation Algorithms on Parallel Virtual Machine.
VLSI Design
C. P. Ravikumar, Vikas Jain, Anurag Dod
2001 Misc conf
Estimating Crosstalk From Vlsi Layouts.
VLSI Design
V. Sankara Subramanian, C. P. Ravikumar
2001 Misc conf
Software Power Optimizations In An Embedded System.
VLSI Design
Vishal Dalal, C. P. Ravikumar
2001 Misc conf
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.
VLSI Design
Vineet Sahula, C. P. Ravikumar
2000 B conf
A Stochastic Framework for Co-synthesis of Real-Time Systems.
LCTES
Shampa Chakraverty, C. P. Ravikumar
2000 J jnl
A scheme for multiple on-chip signature checking for embedded SRAMS.
J. Syst. Archit.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
2000 Misc conf
Efficient Implementation of ADPCM Codec.
VLSI Design
Anil Sharma, C. P. Ravikumar
2000 — conf
Functional Testing of Microprocessors with Graded Fault Coverage.
Asian Test Symposium
Rajesh Kannah, C. P. Ravikumar
2000 Misc conf
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.
VLSI Design
C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma
1999 — conf
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.
Asian Test Symposium
C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra
1999 J jnl
A functional-level testability measure for register-level circuits and its estimation.
Microprocess. Microsystems
C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal
1999 J jnl
Built-in Self Test Based on Multiple On-Chip Signature Checking.
J. Electron. Test.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1999 — conf
Design Issues in Synthesis of Reusable Cores.
Great Lakes Symposium on VLSI
Rohit Sharma, C. P. Ravikumar
1999 Misc conf
Design of WDM Networks for Delay-Bound Multicasting.
HiPC
C. P. Ravikumar, Meeta Sharma, Prachi Jain
1999 Misc conf
Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications.
HiPC
Nishit Narang, Girish Kumar, C. P. Ravikumar
1999 Misc conf
Hierarchical Delay Fault Simulation.
VLSI Design
C. P. Ravikumar, Ajay Mittal
1999 J jnl
High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications.
Parallel Distributed Comput. Pract.
C. P. Ravikumar
1999 Misc conf
Improving the Diagnosability of Digital Circuits.
VLSI Design
C. P. Ravikumar, Manish Sharma, R. K. Patney
1998 — conf
Adaptive Routing Based on Deadlock Recovery.
Euro-Par
Nidhi Agrawal, C. P. Ravikumar
1998 Misc conf
An Evolutionary Approach to System Redesign.
VLSI Design
Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
1998 Misc conf
Efficient algorithms for delay-bounded minimum cost path problem in communication networks.
HiPC
Girish Kumar, Nishit Narang, C. P. Ravikumar
1998 — conf
Evaluating BIST Architectures for Low Power.
Asian Test Symposium
C. P. Ravikumar, N. Satya Prasad
1998 Misc conf
Freedom: Statistical Behavioral Estimation of System Energy and Power.
VLSI Design
Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar
1998 Misc conf
Hybrid Testing Schemes Based on Mutual and Signature Testing.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 Misc conf
On-Chip Signature Checking for Embedded Memories.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 J jnl
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.
J. Electron. Test.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 J jnl
Parallel Methods for Vlsi Layout Design.
IEEE Concurr.
Roman Trobec, C. P. Ravikumar
1998 Misc conf
Performance-driven design and redesign of high-speed local area networks.
HiPC
C. P. Ravikumar, Dilip R. Pandit, Anubhav Mishra
1998 J jnl
SCOAP-based Testability Analysis from Hierarchical Netlists.
VLSI Design
C. P. Ravikumar, Hemant Joshi
1998 J jnl
Source-based delay-bounded multicasting in multimedia networks.
Comput. Commun.
C. P. Ravikumar, Rajneesh Bajpai
1998 Misc conf
Synthesis of Testable RTL Designs.
VLSI Design
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
1998 J jnl
Testability-Driven Layout of Combinational Circuits.
VLSI Design
C. P. Ravikumar, Nikhil Sharma
1997 Misc conf
A Graph-Theoretic Approach for Register File Based Synthesis.
VLSI Design
C. P. Ravikumar, R. Aggarwal, C. Sharma
1997 — conf
A scheme for multiple on-chip signature checking for embedded SRAMs.
ED&TC
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1997 J jnl
Adaptive routing in k-ary n-cubes using incomplete diagnostic information.
Microprocess. Microsystems
C. P. Ravikumar, C. S. Panda
1997 B conf
An Euler Path Based Technique for Deadlock-free Multicasting.
ICPP
Nidhi Agrawal, C. P. Ravikumar
1997 Misc conf
Distributed delay constrained multicast path setup algorithm for high speed networks.
HiPC
Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra
1997 Misc conf
Efficient Implementation of Multiple On-Chip Signature Checking.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1997 Misc conf
Faster Fault Simulation Through Distributed Computing.
VLSI Design
C. P. Ravikumar, Vikas Jain, Anurag Dod
1997 J jnl
Hierarchical Delay Test Generation.
J. Electron. Test.
C. P. Ravikumar, Nitin Agrawal, Parul Agarwal
1997 J jnl
Kautz graphs as attractive logical topologies in multihop lightwave networks.
Comput. Commun.
C. P. Ravikumar, Tarun Rai, Varun Verma
1997 J jnl
Parallelization of symmetry detection algorithms on a network of workstations.
Microprocess. Microsystems
R. Parthiban, C. P. Ravikumar, R. Kakarala, J. Sivaswamy
1997 Misc conf
Rapid Synthesis of Multi-Chip Systems.
VLSI Design
Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
1996 Misc conf
A Novel BIST Architecture With Built-in Self Check.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1996 Misc conf
A genetic algorithm for assembling optical computers using faulty optical arrays.
HiPC
C. P. Ravikumar, Augustine R. Thomas, Abhay Gupta
1996 — conf
Efficient Delay Test Generation for Modular Circuits.
Great Lakes Symposium on VLSI
Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar
1996 Misc conf
Estimation of Power from Module-level Netlists.
VLSI Design
C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora
1996 J jnl
Fault-tolerant routing in multiply twisted cube topology.
J. Syst. Archit.
Nidhi Agrawal, C. P. Ravikumar
1996 Misc conf
Genetic Algorithms for Scan Path Design.
VLSI Design
C. P. Ravikumar, Rajamani Rajarajan
1996 J jnl
Parallel search-and-learn techniques and graph coloring.
Knowl. Based Syst.
C. P. Ravikumar, R. Aggarwal
1996 Misc conf
Synthesis of Testable Pipelined Datapaths Using Genetic Search.
VLSI Design
C. P. Ravikumar, Vikram Saxena
1996 J jnl
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis.
VLSI Design
C. P. Ravikumar, Vikram Saxena
1995 — conf
A STAFAN-like functional testability measure for register-level circuits.
Asian Test Symposium
C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal
1995 Misc conf
HISCOAP: a hierarchical testability analysis tool.
VLSI Design
C. P. Ravikumar, Hemant Joshi
1995 J jnl
Heuristic and neural algorithms for mapping tasks to a reconfigurable array.
Microprocess. Microprogramming
C. P. Ravikumar, Naresh Vedi
1995 J jnl
SHARP: A shape recognition system and its parallel implementation.
Microprocess. Microsystems
C. P. Ravikumar, Rajender Sethi
1994 J jnl
Parallel search-and-learn technique for solving large scale travelling-salesperson problems.
Knowl. Based Syst.
C. P. Ravikumar
1994 Misc conf
Simulated Annealing for Target-Oriented Scan.
VLSI Design
C. P. Ravikumar, Haroon Rasheed
1994 — conf
Star-Graph based multistage interconnection network for ATM switch fabric.
SPDP
C. P. Ravikumar, G. Manimaran
1994 J jnl
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing.
VLSI Design
C. P. Ravikumar, Haroon Rasheed
1993 B conf
A Parallel Search-and-Learn Technique for Solving Large Scale TSP.
ICTAI
C. P. Ravikumar
1993 — conf
Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network.
ICPP (1)
C. P. Ravikumar, A. Kuchlous, G. Manimaran
1993 J jnl
Solving VLSI physical design problems on a vector machine.
Comput. Aided Des.
C. P. Ravikumar
1992 J jnl
Interval partition with bounded overlap.
Comput. Aided Des.
C. P. Ravikumar
1992 J jnl
Parallel techniques for solving large scale travelling salesperson problems.
Microprocess. Microsystems
C. P. Ravikumar
1992 Misc conf
Solving Physical Design Problems on a Vector Machine.
VLSI Design
C. P. Ravikumar
1991 J jnl
VYUHA: A detailed router for multiple routing models.
Integr.
C. P. Ravikumar, Sarma Sastry
1990 J jnl
Performance improvement of simulated annealing algorithms.
Comput. Syst. Sci. Eng.
C. P. Ravikumar, Lalit M. Patnaik
1989 J jnl
A hardware accelerator for hierarchical VLSI routing.
Integr.
C. P. Ravikumar, Sarma Sastry
1989 — conf
Parallel Placement on Hypercube Architecture.
ICPP (3)
C. P. Ravikumar, Sarma Sastry
1988 A* conf
Parallel Placement on Reduced Array Architecture.
DAC
C. P. Ravikumar, Sarma Sastry
1987 B conf
An Architecture for CSP and Its Simulation.
ICPP
C. P. Ravikumar, Lalit M. Patnaik