C. L. Liu - RankMe

140 papers A* 19A 29C 2Misc 3Journal 63Unranked 24

Year	Rank	Type	Title / Venue / Authors
2012	—	`conf`	I attended the nineteenth design automation conference. ISPD C. L. Liu
2005	Misc	`conf`	The High Walls have Crumpled. VLSI Design C. L. Liu
2003	J	`jnl`	Compacting sequences with invariant transition frequencies. ACM Trans. Design Autom. Electr. Syst. Ali Pinar, C. L. Liu
2003	J	`jnl`	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
2003	J	`jnl`	Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2002	J	`jnl`	A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. Ki-Seok Chung, Taewhan Kim, C. L. Liu
2002	—	`conf`	A technology mapping algorithm for CPLD architectures. FPT Shih-Liang Chen, TingTing Hwang, C. L. Liu
2002	J	`jnl`	Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
2002	J	`jnl`	Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
2002	—	`conf`	Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. CICC S. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C. W. Tsai, T. B. Wu, Rich Liu
2002	J	`jnl`	Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu
2001	J	`jnl`	Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. Chau-Shen Chen, TingTing Hwang, C. L. Liu
2001	A	`conf`	Binary decision diagram with minimum expected path length. DATE Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
2001	A*	`conf`	Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
2001	J	`jnl`	G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. Ki-Seok Chung, Taewhan Kim, C. L. Liu
2001	J	`jnl`	Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, C. L. Liu
2000	A*	`conf`	A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC Junhyung Um, Taewhan Kim, C. L. Liu
2000	J	`jnl`	A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prashant Saxena, C. L. Liu
2000	J	`jnl`	An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design Chaeryung Park, Taewhan Kim, C. L. Liu
2000	A	`conf`	Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang
2000	A	`conf`	Noise-aware power optimization for on-chip interconnect. ISLPED Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
1999	—	`conf`	An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) Chaeryung Park, Taewhan Park, C. L. Liu
1999	A*	`conf`	Crosstalk Minimization Using Wire Perturbations. DAC Prashant Saxena, C. L. Liu
1999	A	`conf`	From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. RTSS C. L. Liu
1999	A	`conf`	Implication graph based domino logic synthesis. ICCAD Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
1999	A	`conf`	Logic Transformation for Low Power Synthesis. DATE Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
1999	A	`conf`	Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD Junhyung Um, Taewhan Kim, C. L. Liu
1999	J	`jnl`	Partial Scan with Preselected Scan Signals. IEEE Trans. Computers Peichen Pan, C. L. Liu
1999	Misc	`conf`	The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design Prashant Saxena, Peichen Pan, C. L. Liu
1998	A	`conf`	A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD Prashant Saxena, C. L. Liu
1998	A	`conf`	Architecture driven circuit partitioning. ICCAD Chau-Shen Chen, TingTing Hwang, C. L. Liu
1998	A	`conf`	Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED Ki-Seok Chung, C. L. Liu
1998	A	`conf`	Low power logic synthesis under a general delay model. ISLPED Unni Narayanan, Peichen Pan, C. L. Liu
1998	J	`jnl`	Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. Peichen Pan, C. L. Liu
1998	J	`jnl`	Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peichen Pan, Arvind K. Karandikar, C. L. Liu
1998	A	`conf`	Power invariant vector sequence compaction. ICCAD Ali Pinar, C. L. Liu
1998	J	`jnl`	Register Allocation - A Hierarchical Reduction Approach. J. VLSI Signal Process. Chaeryung Park, Taewhan Kim, C. L. Liu
1997	A*	`conf`	Low Power FPGA Design - A Re-engineering Approach. DAC Chau-Shen Chen, TingTing Hwang, C. L. Liu
1997	A	`conf`	Low power logic synthesis for XOR based circuits. ICCAD Unni Narayanan, C. L. Liu
1997	C	`conf`	Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD Arvind K. Karandikar, Peichen Pan, C. L. Liu
1997	J	`jnl`	Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica Peichen Pan, Sai-keung Dong, C. L. Liu
1997	J	`jnl`	Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
1997	J	`jnl`	Timing-driven placement for regular architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anmol Mathur, C. L. Liu
1996	—	`conf`	A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
1996	—	`conf`	A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. ED&TC Srilata Raman, C. L. Liu, Larry G. Jones
1996	A	`conf`	An algorithm for synthesis of system-level interface circuits. ICCAD Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
1996	J	`jnl`	An integrated algorithm for incremental data path synthesis. J. VLSI Signal Process. Taewhan Kim, C. L. Liu
1996	J	`jnl`	Area Minimization for Hierarchical Floorplans. Algorithmica Peichen Pan, Weiping Shi, C. L. Liu
1996	A*	`conf`	Desensitization for Power Reduction in Sequential Circuits. DAC Xiangfeng Chen, Peichen Pan, C. L. Liu
1996	J	`jnl`	Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
1996	J	`jnl`	Minimum crosstalk channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tong Gao, C. L. Liu
1996	A*	`conf`	Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC Peichen Pan, C. L. Liu
1996	A	`conf`	Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA Peichen Pan, C. L. Liu
1996	—	`conf`	Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. ED&TC Anmol Mathur, C. L. Liu
1996	J	`jnl`	Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. VLSI Design Srilata Raman, C. L. Liu, Larry G. Jones
1995	J	`jnl`	A new approach to the multiport memory allocation problem in data path synthesis. Integr. Taewhan Kim, C. L. Liu
1995	A	`conf`	Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1995	J	`jnl`	Area minimization for floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peichen Pan, C. L. Liu
1995	J	`jnl`	Minimum crosstalk switchbox routing. Integr. Tong Gao, C. L. Liu
1995	J	`jnl`	Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. IEEE Trans. Parallel Distributed Syst. Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu
1995	A*	`conf`	Partial Scan with Pre-selected Scan Signals. DAC Peichen Pan, C. L. Liu
1995	A	`conf`	Re-engineering of timing constrained placements for regular architectures. ICCAD Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1994	—	`conf`	A delay driven FPGA placement algorithm. EURO-DAC Srilata Raman, C. L. Liu, Larry G. Jones
1994	J	`jnl`	A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
1994	A	`conf`	Area minimization for hierarchical floorplans. ICCAD Peichen Pan, Weiping Shi, C. L. Liu
1994	A	`conf`	Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD Anmol Mathur, C. L. Liu
1994	A	`conf`	Minimum crosstalk switchbox routing. ICCAD Tong Gao, C. L. Liu
1994	A*	`conf`	Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. DAC Yachyang Sun, C. L. Liu
1993	A	`conf`	Minimum crosstalk channel routing. ICCAD Tong Gao, C. L. Liu
1993	J	`jnl`	Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. IEEE Trans. Software Eng. Wei-Kuan Shih, Jane W.-S. Liu, C. L. Liu
1993	A*	`conf`	Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC Peichen Pan, Sai-keung Dong, C. L. Liu
1993	J	`jnl`	Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bryan Preas, C. L. Liu
1993	—	`conf`	Register allocation for data flow graphs with conditional branches and loops. EURO-DAC Chaeryung Park, Taewhan Kim, C. L. Liu
1993	A	`conf`	Routing for symmetric FPGAs and FPICs. ICCAD Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
1993	A*	`conf`	Utilization of Multiport Memories in Data Path Synthesis. DAC Taewhan Kim, C. L. Liu
1992	A*	`conf`	A Performance Driven Macro-Cell Placement Algorithm. DAC Tong Gao, Pravin M. Vaidya, C. L. Liu
1992	C	`conf`	An Area Minimizer for Floorplans with L-Shaped Regions. ICCD Yachyang Sun, C. L. Liu
1992	A	`conf`	Area minimization for general floorplans. ICCAD Peichen Pan, C. L. Liu
1992	—	`conf`	Fundamentals of Real-Time Scheduling (Extended Abstract). NATO ASI RTC C. L. Liu
1991	A	`conf`	A Channel Router for Single Layer Customization Technology. ICCAD Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu
1991	A	`conf`	A New Performance Driven Placement Algorithm. ICCAD Tong Gao, Pravo M. Vaidya, C. L. Liu
1991	A	`conf`	A Scheduling Algorithm for Conditional Resource Sharing. ICCAD Taewhan Kim, Jane W.-S. Liu, C. L. Liu
1991	J	`jnl`	Disjoint Covers in Replicated Heterogeneous Arrays. SIAM J. Discret. Math. Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu
1991	J	`jnl`	Minimum fault covering in reconfigurable arrays. Integr. Nany Hasan, C. L. Liu
1991	J	`jnl`	On the k-layer planar subset and topological via minimization problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, C. L. Liu
1990	—	`conf`	Fault covers in reconfigurable PLAs. FTCS Nany Hasan, C. L. Liu
1990	A*	`conf`	General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC Jason Cong, Bryan Preas, C. L. Liu
1990	—	`conf`	On the k-layer planar subset and via minimization problems. EURO-DAC Jason Cong, C. L. Liu
1990	J	`jnl`	Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, C. L. Liu
1990	J	`jnl`	PLA logic minimization by simulated annealing. Integr. Xianjin Yao, C. L. Liu
1990	—	`conf`	Solution of a module orientation and rotation problem. EURO-DAC Xianjin Yao, C. L. Liu
1989	J	`jnl`	A new approach to the pin assignment problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xianjin Yao, Masaaki Yamada, C. L. Liu
1989	J	`jnl`	An enhanced bottom-up algorithm for floorplan design. Integr. Thomas R. Mueller, D. F. Wong, C. L. Liu
1989	A	`conf`	Constrained floorplan design for flexible blocks. ICCAD Sai-keung Dong, Jason Cong, C. L. Liu
1989	J	`jnl`	Floorplan Design of VLSI Circuits. Algorithmica D. F. Wong, C. L. Liu
1989	J	`jnl`	Generalized latin squares I. Discret. Appl. Math. Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal
1989	A*	`conf`	Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. DAC Ran Libeskind-Hadas, C. L. Liu
1988	A*	`conf`	A New Approach to the Pin Assignment Problem. DAC Xianji Yao, Masaaki Yamada, C. L. Liu
1988	J	`jnl`	A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Martin D. F. Wong, C. L. Liu
1988	A	`conf`	A new formulation of yield enhancement problems for reconfigurable chips. ICCAD Nany Hasan, Jason Cong, C. L. Liu
1988	—	`conf`	Minimum fault coverage in reconfigurable arrays. FTCS Nany Hasan, C. L. Liu
1988	A	`conf`	Over-the-cell channel routing. ICCAD Jingsheng Cong, C. L. Liu
1987	J	`jnl`	Algorithms for permutation channel routing. Integr. H. W. Leong, C. L. Liu
1987	A*	`conf`	Array Optimization for VLSI Synthesis. DAC D. F. Wong, C. L. Liu
1986	A*	`conf`	A new algorithm for floorplan design. DAC D. F. Wong, C. L. Liu
1986	J	`jnl`	An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. J. Algorithms James L. Lewandowski, C. L. Liu, Jane W.-S. Liu
1986	J	`jnl`	Compacted channel routing with via placement restrictions. Integr. D. F. Wong, C. L. Liu
1985	J	`jnl`	Permutation Representation of k-Ary Trees. Theor. Comput. Sci. Prakash V. Ramanan, C. L. Liu
1984	J	`jnl`	A Personnel Assignment Problem. J. Algorithms Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu
1984	A*	`conf`	A branch and bound algorithm for optimal pla folding. DAC James L. Lewandowski, C. L. Liu
1984	J	`jnl`	Bipartite Folding and Partitioning of a PLA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jack R. Egan, C. L. Liu
1983	J	`jnl`	(g 0, g 1, ... g k)-Trees and Unary OL Systems. Theor. Comput. Sci. D. T. Lee, C. L. Liu, C. K. Wong
1983	A*	`conf`	A new channel routing problem. DAC Hon Wai Leong, C. L. Liu
1983	J	`jnl`	On a Periodic Maintenance Problem. Oper. Res. Lett. W.-D. Wei, C. L. Liu
1983	J	`jnl`	SS/TDMA Time Slot Assignment with Restricted Switching Modes. IEEE Trans. Commun. James L. Lewandowski, Jane W.-S. Liu, C. L. Liu
1982	A*	`conf`	Optimal bipartite folding of PLA. DAC Jack R. Egan, C. L. Liu
1982	J	`jnl`	Scheduling with Slack Time. Acta Informatica C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman
1980	—	`conf`	Generation of trees. CLAAP C. L. Liu
1978	J	`jnl`	A generalization of Ramsey theory for graphs. Discret. Math. K. M. Chung, C. L. Liu
1978	J	`jnl`	On a Real-Time Scheduling Problem. Oper. Res. Sudarshan K. Dhall, C. L. Liu
1978	J	`jnl`	Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. Acta Informatica Jane W.-S. Liu, C. L. Liu
1976	Misc	`conf`	Deterministic Job Scheduling in Computing Systems. Performance C. L. Liu
1975	J	`jnl`	Sperner's theorem on maximal-sized antichains and its generalization. Discret. Math. C. L. Liu
1974	—	`conf`	Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. IFIP Congress Jane W.-S. Liu, C. L. Liu
1974	—	`conf`	On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. Sagamore Computer Conference N. F. Chen, C. L. Liu
1973	J	`jnl`	A construction scheme for linear and non-linear codes. Discret. Math. C. L. Liu, B. G. Ong, Gregory R. Ruth
1973	—	`conf`	A drum scheduling algorithm. Automatentheorie und Formale Sprachen C. K. Wong, C. L. Liu, J. Apter
1973	—	`conf`	Analysis of sorting algorithms. AFIPS National Computer Conference C. L. Liu
1973	J	`jnl`	Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. J. ACM C. L. Liu, James W. Layland
1972	J	`jnl`	Analysis and Synthesis of Sorting Algorithms. SIAM J. Comput. C. L. Liu
1972	J	`jnl`	Complementary sets of sequences. IEEE Trans. Inf. Theory Chin-Chong Tseng, C. L. Liu
1972	—	`conf`	Optimal Scheduling on Multi-Processor Computing Systems SWAT C. L. Liu
1971	—	`conf`	Analysis of Sorting Algorithms SWAT C. L. Liu
1969	J	`jnl`	A Note on Definite Stochastic Sequential Machines Inf. Control. C. L. Liu
1969	J	`jnl`	Lattice Functions, Pair Algebras, and Finite-State Machines. J. ACM C. L. Liu
1967	—	`conf`	The design and implementation of a table driven compiler system. AFIPS Spring Joint Computing Conference C. L. Liu, G. D. Chang, R. E. Marks
1966	—	`conf`	Pair Algebra and Its Application SWAT C. L. Liu
1966	J	`jnl`	Some algebraic properties of multi-threshold functions. IEEE Trans. Electron. Comput. C. L. Liu
1964	—	`conf`	Sequential-machine realization using feedback shift registers SWCT C. L. Liu
1964	J	`jnl`	kth-Order Finite Automaton. IEEE Trans. Electron. Comput. C. L. Liu