C. Bernard Shung

23 papers A* 1C 3Misc 2Journal 14Unranked 3
YearRankTypeTitle / Venue / Authors
2008 J jnl
A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset.
IEEE Micro
Jeffrey M. Gilbert, Chinh H. Doan, Sohrab Emami, C. Bernard Shung
2003 J jnl
A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services.
IEEE Trans. Veh. Technol.
Kuen-Rong Lo, Chung-Ju Chang, C. Bernard Shung
2001 J jnl
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications.
IEEE J. Solid State Circuits
Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee
2000 J jnl
A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems.
IEEE Trans. Veh. Technol.
Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung
2000 J jnl
Two systolic architectures for modular multiplication.
IEEE Trans. Very Large Scale Integr. Syst.
Wei-Chang Tsai, C. Bernard Shung, Sheng-Jyh Wang
1999 J jnl
New serial architecture for the Berlekamp-Massey algorithm.
IEEE Trans. Commun.
Hsie-Chia Chang, C. Bernard Shung
1998 — conf
A (208, 192;8) Reed-Solomon decoder for DVD application.
ICC
Hsie-Chia Chang, C. Bernard Shung
1998 J jnl
A combined channel assignment mechanism for hierarchical cellular systems.
Comput. Commun.
Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung
1997 J jnl
Event-Driven Power Estimation of CMOS Circuits.
J. Circuits Syst. Comput.
Wei-Chang Tsai, C. Bernard Shung
1997 J jnl
Quasi-pushout cell discarding.
IEEE Commun. Lett.
Yu-Sheng Lin, C. Bernard Shung
1997 — conf
Reactive Bandwidth Arbitration for Priority and Multicasting Control in ATM Switching.
ICC (3)
Shu-Jen Fang, Yu-Sheng Lin, Shan-Chieh Yang, C. Bernard Shung
1996 A* conf
Queue Management for Shared Buffer and Shared Multi-Buffer ATM Switches.
INFOCOM
Yu-Sheng Lin, C. Bernard Shung
1994 C conf
Fault-Tolerant Architectures for Shared Buffer Memory Switch.
ISCAS
Yeong-Fong Lin, C. Bernard Shung
1993 C conf
A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
ISCAS
Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
1993 J jnl
Area-efficient architectures for the Viterbi algorithm II. Applications.
IEEE Trans. Commun.
C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar
1993 J jnl
Area-efficient architectures for the Viterbi algorithm. I. Theory.
IEEE Trans. Commun.
C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar
1993 J jnl
Generalized trace-back techniques for survivor memory management in the Viterbi algorithm.
J. VLSI Signal Process.
Robert Cypher, C. Bernard Shung
1992 — conf
Crossing distribution.
EURO-DAC
Deborah C. Wang, C. Bernard Shung
1991 J jnl
A 30-MHz trellis codec chip for partial-response channels.
IEEE J. Solid State Circuits
C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed
1991 J jnl
An integrated CAD system for algorithm-specific IC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen
1991 Misc conf
Exact bounds for Viterbi detector path metric differences.
ICASSP
Paul H. Siegel, C. Bernard Shung, Thomas D. Howell, Hemant K. Thapar
1991 Misc conf
General in-place scheduling for the Viterbi algorithm.
ICASSP
Horng-Dar Lin, C. Bernard Shung
1990 C conf
Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels.
ICCD
C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed