Béla Fehér

16 papers A 1B 2C 1Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2011 B conf
Molecular Docking on FPGA and GPU Platforms.
FPL
Imre Pechan, Béla Fehér
2009 — conf
LOGSYS: A simple tool for complex student projects.
MSE
Béla Fehér, Tamás Raikovich, György Dancsi, Péter Laczkó
2008 J jnl
High-Performance Timing-Driven Rank Filter.
VLSI Design
Péter Szántó, Gábor Szedö, Béla Fehér
2006 — conf
Acoustic Source Localization Fusing Sparse Direction of Arrival Estimates.
WISES
Ákos Lédeczi, Gergely Kis, Béla Fehér, Péter Völgyesi, György Balogh
2006 — conf
High Performance Timing-Driven Rank Filter.
ICECS
Péter Szántó, Béla Fehér, Gábor Szedö
2005 J jnl
Heuristic Automation for Decluttering Tactical Displays.
Hum. Factors
Mark F. St. John, Harvey S. Smallman, Daniel I. Manes, Béla Fehér, Jeffrey G. Morrison
2004 — conf
High performance visibility testing with screen segmentation.
ESTIMedia
Péter Szántó, Béla Fehér
2003 C conf
3D rendering using FPGAs.
VLSI-SOC
Péter Szántó, Béla Fehér
2003 A conf
Dependability Analysis: A New Application for Run-Time Reconfiguration.
IPDPS
Régis Leveugle, Lörinc Antoni, Béla Fehér
2003 J jnl
Using run-time reconfiguration for fault injection applications.
IEEE Trans. Instrum. Meas.
Lörinc Antoni, Régis Leveugle, Béla Fehér
2002 — conf
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT
Lörinc Antoni, Régis Leveugle, Béla Fehér
2000 — conf
A Full-Parallel Digital Implementation for Pre-Trained NNs.
IJCNN (2)
Tamás Szabó, Lörinc Antoni, Gábor Horváth, Béla Fehér
2000 — conf
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT
Lörinc Antoni, Régis Leveugle, Béla Fehér
1998 B conf
Cost Effective 2×2 Inner Product Processors.
FPL
Béla Fehér, Gábor Szedö
1998 — conf
Neural network implementation using distributed arithmetic.
KES (3)
Tamás Szabó, Béla Fehér, Gábor Horváth
1993 J jnl
Efficient synthesis of distributed vector multipliers.
Microprocess. Microprogramming
Béla Fehér