Byung-Gook Park

56 papers A 1B 1Journal 51Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory.
IEEE Trans. Neural Networks Learn. Syst.
Dongseok Kwon, Sung Yun Woo, Joon Hwang, Hyeongsu Kim, Jong-Ho Bae, Wonjun Shin, Byung-Gook Park, Jong-Ho Lee
2023 J jnl
Data-driven multi-objective optimization with neural network-based sensitivity analysis for semiconductor devices.
Eng. Appl. Artif. Intell.
Min-Hye Oh, Kitae Lee, Sihyun Kim, Byung-Gook Park
2023 J jnl
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application.
Appl. Intell.
Kannan Udaya Mohanan, Seongjae Cho, Byung-Gook Park
2022 J jnl
4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array.
Adv. Intell. Syst.
Sungjoon Kim, Jinwoo Park, Tae-Hyeon Kim, Kyungho Hong, Yeongjin Hwang, Byung-Gook Park, Hyungjin Kim
2022 J jnl
A Fast Weight Transfer Method for Real-Time Online Learning in RRAM-Based Neuromorphic System.
IEEE Access
Min-Hwi Kim, Sin-Hyung Lee, Sungjun Kim, Byung-Gook Park
2022 — conf
First Demonstration of 1-bit Erase in Vertical NAND Flash Memory.
VLSI Technology and Circuits
Honam Yoo, Jong-Won Back, Nam-Hun Kim, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
2022 J jnl
On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding.
IEEE Access
Jiseong Im, Jaehyeon Kim, Honam Yoo, Jong-Won Baek, Dongseok Kwon, Seongbin Oh, Jangsaeng Kim, Joon Hwang, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks.
Adv. Intell. Syst.
Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min-Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks.
Adv. Intell. Syst.
Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment.
IEEE Access
Won-Mook Kang, Dongseok Kwon, Sung Yun Woo, Soochang Lee, Honam Yoo, Jangsaeng Kim, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality.
Neurocomputing
Jangsaeng Kim, Dongseok Kwon, Sung Yun Woo, Won-Mook Kang, Soochang Lee, Seongbin Oh, Chul-Heung Kim, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation.
IEEE Access
Seunghwan Song, Bosung Jeon, Sungmin Hwang, Myung-Hyun Baek, Jong-Ho Lee, Byung-Gook Park
2021 J jnl
Low-Power Adaptive Integrate-and-Fire Neuron Circuit Using Positive Feedback FET Co-Integrated With CMOS.
IEEE Access
Min-Woo Kwon, Kyungchul Park, Byung-Gook Park
2021 J jnl
On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm.
Neural Comput. Appl.
Jangsaeng Kim, Dongseok Kwon, Sung Yun Woo, Won-Mook Kang, Soochang Lee, Seongbin Oh, Chul-Heung Kim, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
2021 J jnl
Pulse-Width Modulation Neuron Implemented by Single Positive-Feedback Device.
CoRR
Sung Yun Woo, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae
2021 J jnl
Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array.
IEEE Access
Dayoung Kim, Tae-Hyeon Kim, Yun-Yeong Choi, Geun Ho Lee, Jungwon Lee, Wookyung Sun, Byung-Gook Park, Hyungjin Kim, Hyungsoon Shin
2021 J jnl
Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model.
IEEE Access
Seongbin Oh, Soochang Lee, Sung Yun Woo, Dongseok Kwon, Jiseong Im, Joon Hwang, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
2020 J jnl
Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning.
IEEE Access
Dong-Hyun Ryu, Tae-Hyung Kim, Taejin Jang, Junsu Yu, Jong-Ho Lee, Byung-Gook Park
2020 J jnl
Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy.
Neurocomputing
Hyeongsu Kim, Jong-Ho Bae, Suhwan Lim, Sungtae Lee, Young-Tak Seo, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
2020 J jnl
Insertion of Ag Layer in TiN/SiN
IEEE Access
Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Kyungho Hong, Chae Soo Kim, Sungjun Kim, Seongjae Cho, Byung-Gook Park
2020 J jnl
Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems.
IEEE Access
Sung Yun Woo, Dongseok Kwon, Nagyong Choi, Won-Mook Kang, Young-Tak Seo, Min Kyu Park, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
2020 J jnl
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering.
IEEE Access
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
2019 B conf
A Spiking Neural Network with a Global Self-Controller for Unsupervised Learning Based on Spike-Timing-Dependent Plasticity Using Flash Memory Synaptic Devices.
IJCNN
Won-Mook Kang, Chul-Heung Kim, Soochang Lee, Sung Yun Woo, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
2019 J jnl
Adaptive learning rule for hardware-based deep neural networks using electronic synapse devices.
Neural Comput. Appl.
Suhwan Lim, Jong-Ho Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
2019 J jnl
Reversible nonvolatile and threshold switching characteristics in Cu/high-k/Si devices.
IEICE Electron. Express
Chandreswar Mahata, Wonwoo Kim, Shiwhan Kim, Muhammad Ismail, Min-Hwi Kim, Sungjun Kim, Byung-Gook Park
2019 J jnl
Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors.
Sensors
Mihee Uhm, Jin-Moo Lee, Jieun Lee, Jung Han Lee, Sungju Choi, Byung-Gook Park, Dong Myong Kim, Sung-Jin Choi, Hyun-Sun Mo, Yong-Joo Jeong, Dae Hwan Kim
2018 J jnl
Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array.
CoRR
Soochang Lee, Chul-Heung Kim, Seongbin Oh, Byung-Gook Park, Jong-Ho Lee
2017 J jnl
Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.
CoRR
Suhwan Lim, Jong-Ho Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, Byung-Gook Park, Jong-Ho Lee
2016 J jnl
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell.
IEICE Trans. Electron.
Sungjun Kim, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
2015 — conf
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect.
ISCE
Mina Yun, Seongjae Cho, Sae-Kyoung Kang, Sunghun Jung, Byung-Gook Park
2015 J jnl
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals.
IEICE Trans. Electron.
Sungjun Kim, Sunghun Jung, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
2014 J jnl
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access.
IEICE Electron. Express
Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park
2013 J jnl
L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications.
IEICE Trans. Electron.
Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park
2013 J jnl
Novel Tunneling Field-Effect Transistor with Sigma-Shape Embedded SiGe Sources and Recessed Channel.
IEICE Trans. Electron.
Min-Chul Sun, Sang Wan Kim, Garam Kim, Hyun Woo Kim, Hyungjin Kim, Byung-Gook Park
2012 J jnl
Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors.
IEICE Trans. Electron.
Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim, Garam Kim, Hyungjin Kim, Byung-Gook Park
2012 J jnl
Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics.
IEICE Trans. Electron.
Kyung-Chang Ryoo, Jeong-Hoon Oh, Sunghun Jung, Hyungjin Kim, Byung-Gook Park
2012 J jnl
Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer).
IEICE Trans. Electron.
Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Hyungjin Kim, Byung-Gook Park
2012 J jnl
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance.
IEICE Electron. Express
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park, James S. Harris Jr.
2012 J jnl
Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using
IEICE Trans. Electron.
Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim, Garam Kim, Byung-Gook Park
2011 J jnl
A New 1T DRAM Cell: Cone Type 1T DRAM Cell.
IEICE Trans. Electron.
Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park
2011 J jnl
The novel SCR-based ESD protection with low triggering and high holding voltages.
Microelectron. J.
Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin
2010 J jnl
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices.
IEICE Trans. Electron.
Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park
2010 J jnl
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer.
IEICE Trans. Electron.
Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park
2009 J jnl
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.
IEICE Trans. Electron.
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2009 J jnl
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design.
IEICE Trans. Electron.
Jongwook Jeon, Ickhyun Song, Jong Duk Lee, Byung-Gook Park, Hyungcheol Shin
2009 J jnl
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).
IEICE Trans. Electron.
Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2009 J jnl
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era.
Microelectron. J.
Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho
2009 J jnl
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation.
IEICE Trans. Electron.
Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park
2009 J jnl
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory.
IEICE Trans. Electron.
Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2008 J jnl
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.
IEICE Trans. Electron.
Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park
2008 J jnl
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Trans. Electron.
Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2007 J jnl
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Trans. Electron.
Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2007 J jnl
Design and Simulation of Asymmetric MOSFETs.
IEICE Trans. Electron.
Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park
2004 J jnl
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements.
Microelectron. Reliab.
Hyuck In Kwon, In Man Kang, Byung-Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn, Yong Hee Lee
2003 — conf
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
ISMVL
Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park
2003 A conf
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.
ISLPED
Woo Young Choi, Jong Duk Lee, Byung-Gook Park