Byung-Do Yang

36 papers C 3Journal 25Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Camouflaged Logic Gates Using Threshold-Voltage-Defined Memory Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Min-Woo Kim, Jae-Mun Oh, Byung-Do Yang
2023 J jnl
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.
Sensors
Hyeong-Ju Kang, Byung-Do Yang
2020 J jnl
0.3-V RC-to-Digital Converter Using a Negative Charge-Pump Switch.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Byung-Do Yang
2020 J jnl
A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Byung-Do Yang
2020 J jnl
A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit.
IEEE Trans. Circuits Syst.
Ki-Chan Woo, Byung-Do Yang
2020 J jnl
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
2020 J jnl
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering.
IEEE Access
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
2019 — conf
A Voltage-Mode Buck Converter With a Reduced Type-I Compensation Capacitor Using an Error-Amplifier Current-Sampling Scheme.
ICEIC
Dae-Jin Kim, Tae-Hyeong Kim, Hyeon-Sam Shin, Bo-Seok Seo, Mi-Jeong Kim, Byung-Do Yang
2019 J jnl
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
2019 J jnl
DC-DC Buck Converter Using Analog Coarse-Fine Self-Tracking Zero-Current Detection Scheme.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Jae-Mun Oh, Byung-Do Yang
2019 — conf
Depth Map Estimation Model with Efficient Feature Extraction Module.
ICEIC
Soo-Yeon Shin, Dong-Myung Kim, Byung-Do Yang, Chansik Park, Jae-Won Suh
2019 — conf
Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register.
ICEIC
Tae-Hyeong Kim, Dae-Jin Kim, Hyeon-Sam Shin, Sang-Ho Lee, Jae-Won Suh, Byung-Do Yang
2018 J jnl
Low-Area TCAM Using A Don't Care Reduction Scheme.
IEEE J. Solid State Circuits
Ki-Chan Woo, Byung-Do Yang
2017 J jnl
Extracting the Source Code Context to Predict Import Changes using GPES.
KSII Trans. Internet Inf. Syst.
Jaekwon Lee, Kisub Kim, Yonghyeon Lee, Jang-Eui Hong, Young-Hoon Seo, Byung-Do Yang, Woosung Jung
2015 J jnl
Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme.
IEEE J. Solid State Circuits
Byung-Do Yang
2015 J jnl
Low-Power and Area-Efficient Shift Register Using Pulsed Latches.
IEEE Trans. Circuits Syst. I Regul. Pap.
Byung-Do Yang
2014 J jnl
250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit.
IEEE Trans. Circuits Syst. II Express Briefs
Byung-Do Yang
2012 J jnl
Low-Power Time Deinterleaver for ISDB-T Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeong-Ju Kang, Byung-Do Yang
2011 J jnl
A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Byung-Do Yang
2011 J jnl
A Low Power Content Addressable Memory Using Low Swing Search Lines.
IEEE Trans. Circuits Syst. I Regul. Pap.
Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang
2011 J jnl
Area-Efficient Prefilter Architecture for a CDMA Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang
2010 J jnl
A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.
IEEE J. Solid State Circuits
Byung-Do Yang
2009 C conf
A Fast-switching Current-pulse Driver for LED Backlight.
ISCAS
Jang-Su Kim, Yong-Kyu Lee, Jee-Sue Lee, Young-Kyu Shin, Jung-Hyun Tark, Keun-Chul Ryu, Byung-Do Yang
2008 C conf
A highly accurate BiCMOS cascode current mirror for wide output voltage range.
ISCAS
Byung-Do Yang, Jang-Su Kim, Jin-Kuk Yun, Yong-Kyu Lee, Jee-Sue Lee
2007 C conf
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme.
ISCAS
Byung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, Byoung-Gon Yu
2006 J jnl
A low-power ROM using single charge-sharing capacitor and hierarchical bit line.
IEEE Trans. Very Large Scale Integr. Syst.
Byung-Do Yang, Lee-Sup Kim
2005 J jnl
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver.
IEEE J. Solid State Circuits
Byung-Do Yang, Lee-Sup Kim
2005 J jnl
A low-power SRAM using hierarchical bit line and local sense amplifiers.
IEEE J. Solid State Circuits
Byung-Do Yang, Lee-Sup Kim
2004 J jnl
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter.
IEEE J. Solid State Circuits
Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu
2004 — conf
An error pattern ROM compression method for continuous data.
ISCAS (2)
Byung-Do Yang, Lee-Sup Kim
2003 — conf
A low power charge sharing ROM using dummy bit lines.
ISCAS (5)
Byung-Do Yang, Lee-Sup Kim
2003 J jnl
A low-power ROM using charge recycling and charge sharing techniques.
IEEE J. Solid State Circuits
Byung-Do Yang, Lee-Sup Kim
2003 J jnl
A low-power charge-recycling ROM architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Byung-Do Yang, Lee-Sup Kim
2002 — conf
A ROM compression method for continuous data.
CICC
Byung-Do Yang, Lee-Sup Kim
2002 — conf
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.
ISCAS (5)
Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
2001 — conf
A low power charge-recycling ROM architecture.
ISCAS (4)
Byung-Do Yang, Lee-Sup Kim