ByongChan Lim

11 papers A* 2A 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2020 J jnl
Fast FPGA emulation of analog dynamics in digitally-driven systems.
CoRR
Steven Herbst, ByongChan Lim, Mark Horowitz
2020 — conf
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.
VLSI Circuits
Sung-Jin Kim, Zachary A. Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
2020 J jnl
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.
CoRR
Sung-Jin Kim, Zachary A. Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
2019 J jnl
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification.
IEEE Trans. Very Large Scale Integr. Syst.
ByongChan Lim, Mark Horowitz
2018 A conf
Fast FPGA emulation of analog dynamics in digitally-driven systems.
ICCAD
Steven Herbst, ByongChan Lim, Mark Horowitz
2016 — conf
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture.
VLSI Circuits
Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz
2016 J jnl
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.
IEEE Trans. Circuits Syst. I Regul. Pap.
ByongChan Lim, Mark Horowitz
2015 J jnl
Digital Analog Design: Enabling Mixed-Signal System Validation.
IEEE Des. Test
ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz
2010 A* conf
An efficient test vector generation for checking analog/mixed-signal functional models.
DAC
ByongChan Lim, Jaeha Kim, Mark A. Horowitz
2010 A* conf
Fortifying analog models with equivalence checking and coverage analysis.
DAC
Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao
2009 — conf
Leveraging designer's intent: A path toward simpler analog CAD tools.
CICC
Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz