Byeong Yong Kong

34 papers B 1C 6Misc 2Journal 17Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
Fault-Tolerant IDMA Multiuser Detector Based on Fault Injection Analysis of Internal Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Byeong Yong Kong
2025 C conf
Generalized Shifting-Based PAPR Reduction Architecture for Discrete Multitone Systems.
ISCAS
Byeong Yong Kong
2025 — conf
Scalable VLSI Architectures for Pattern Matching in Serial Data Stream.
ICEIC
Byeong Yong Kong
2024 J jnl
A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jaehee Kim, Sangil Han, Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
2024 C conf
Constrained Sorter Design using Zero-One Principle.
ISCAS
Sangil Han, Jaehee Kim, Dongyun Kam, Byeong Yong Kong, Mijung Kim, Young-Seok Kim, Youngjoo Lee
2024 J jnl
Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange.
IEEE Trans. Very Large Scale Integr. Syst.
Byeong Yong Kong
2024 — conf
Statistical Analysis of Bitwise Early Termination for Iterative Multiuser Detection in IDMA Systems.
ICEIC
Byeong Yong Kong
2023 — conf
An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency.
ICEIC
Byeong Yong Kong, Hoyoung Yoo, Youngjoo Lee
2023 J jnl
Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
2022 — conf
A 1.1μs 1.56Gb/s/mm
VLSI Technology and Circuits
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
2022 J jnl
A 97-mW Bitwise-Early-Terminating Multiuser Detector for IDMA Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Byeong Yong Kong
2022 J jnl
Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing.
IEEE Trans. Circuits Syst. II Express Briefs
Sangbu Yun, Byeong Yong Kong, Youngjoo Lee
2021 J jnl
Bitwise Early Termination of Multiuser Detection for IDMA Systems.
IEEE Commun. Lett.
Byeong Yong Kong
2021 Misc conf
Low-Latency Polar Decoder Using Overlapped SCL Processing.
ICASSP
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
2021 J jnl
Real-Time SSDLite Object Detection on FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park
2020 C conf
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access.
ISCAS
Byeong Yong Kong, In-Cheol Park
2020 J jnl
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access.
IEEE Trans. Circuits Syst. II Express Briefs
Byeong Yong Kong, In-Cheol Park
2020 C conf
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis.
ISCAS
Byeong Yong Kong, Jooseung Lee, In-Cheol Park
2020 J jnl
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Byeong Yong Kong, Jooseung Lee, In-Cheol Park
2020 C conf
Improved Parallel-IDMA Architecture with Low-Complexity Elementary Signal Estimators.
ISCAS
Byeong Yong Kong
2020 J jnl
Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jaewoong Choi, Byeong Yong Kong, In-Cheol Park
2020 C conf
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
ISCAS
Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, Youngjoo Lee
2019 — conf
Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns.
ICC
Byeong Yong Kong, In-Cheol Park
2018 J jnl
A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading.
IEEE J. Solid State Circuits
Byeong Yong Kong, In-Cheol Park
2018 — conf
Efficient Implementation of Multiple Interleavers in IDMA for 5G.
ISOCC
Byeong Yong Kong, In-Cheol Park
2018 — conf
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors.
ICECS
Byeong Yong Kong, Jaehwan Jung, In-Cheol Park
2017 J jnl
Improved Sorting Architecture for K-Best MIMO Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Byeong Yong Kong, In-Cheol Park
2016 J jnl
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park
2016 B conf
Low-complexity symbol detection for massive MIMO uplink based on Jacobi method.
PIMRC
Byeong Yong Kong, In-Cheol Park
2015 Misc conf
Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation.
ICASSP
Byeong Yong Kong, In-Cheol Park
2014 J jnl
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park
2013 — conf
Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors.
VTC Spring
Byeong Yong Kong, In-Cheol Park
2013 J jnl
Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization.
IEEE Commun. Lett.
Byeong Yong Kong, In-Cheol Park
2012 J jnl
FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Byeong Yong Kong, In-Cheol Park