Burhan Khurshid

12 papers Misc 2Journal 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
FPGA-Based Resource-Optimal Approximate Multiplier for Error-Resilient Applications.
Int. J. Circuit Theory Appl.
Burhan Khurshid
2025 J jnl
High-performance CORDIC-based approximate MAC architectures for FPGA platforms.
Integr.
Burhan Khurshid
2021 J jnl
An Efficient Fixed-Point Multiplier Based on CORDIC Algorithm.
J. Circuits Syst. Comput.
Burhan Khurshid, Javeed Jeelani Khan
2018 J jnl
Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs.
J. Circuits Syst. Comput.
Burhan Khurshid
2017 J jnl
An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs.
Circuits Syst. Signal Process.
Burhan Khurshid, Roohie Naaz Mir
2017 J jnl
Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs.
J. Circuits Syst. Comput.
Burhan Khurshid, Roohie Naaz Mir
2017 J jnl
LUT based realization of fixed-point multipliers targeting state-of-art FPGAs.
Des. Autom. Embed. Syst.
Burhan Khurshid
2017 J jnl
Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs.
J. Signal Process. Syst.
Burhan Khurshid
2016 J jnl
Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.
Int. J. High Perform. Syst. Archit.
Burhan Khurshid, Roohie Naaz Mir
2015 J jnl
High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs.
Int. J. Reconfigurable Comput.
Burhan Khurshid, Roohie Naaz Mir
2015 Misc conf
High Efficiency Generalized Parallel Counters for Xilinx FPGAs.
HiPC
Burhan Khurshid, Roohie Naaz Mir
2014 Misc conf
A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms.
VLSID
Burhan Khurshid, Roohie Naaz Mir